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@RISCY-Lib

RISCY-Lib

README.md

RISCY-Lib

RISCY-Lib is an opensource collection of RTL (mainly SystemVerilog) design and verification Tools.

Interfaces

  • interfaces
    • A repo which contains a set of common SystemVerilog interfaces for Design and Verification

UVM Packages

Agents

Layering Agents

Misc

RTL Modules

  • uart2sram
    • A module which converts the UART2Register Packet to an SRAM interface

Popular repositories Loading

  1. rtlpy rtlpy Public

    A Library of Python Utilities for RTL Design

    Python

  2. Coding-Standards Coding-Standards Public

    A collection of the Coding Standards for use in RISCY-Lib projects

    TeX

  3. uart_agent uart_agent Public

    A UART UVM Agent

    SystemVerilog

  4. uvm_utils uvm_utils Public

    A collection of utility classes and headers for use in a UVM testbench

    SystemVerilog

  5. GeneratedUniversalTestSuite GeneratedUniversalTestSuite Public

    GeneratedUniversalTestSuite (GUTS) is a python library and tool suite which is designed to automate and simplify UVM test creation and documentation

    Python

  6. i2c_agent i2c_agent Public

    SystemVerilog

Repositories

Showing 10 of 13 repositories
  • rtlpy Public

    A Library of Python Utilities for RTL Design

    RISCY-Lib/rtlpy’s past year of commit activity
    Python 0 GPL-3.0 0 1 0 Updated Jun 12, 2024
  • interfaces Public
    RISCY-Lib/interfaces’s past year of commit activity
    SystemVerilog 0 LGPL-2.1 0 0 0 Updated May 25, 2024
  • .github Public
    RISCY-Lib/.github’s past year of commit activity
    0 GPL-2.0 0 0 0 Updated May 22, 2024
  • mavsec Public

    A tool for the creation of JasperGold SVP principle tcl files.

    RISCY-Lib/mavsec’s past year of commit activity
    Python 0 GPL-3.0 0 7 0 Updated Apr 23, 2024
  • uart2sram Public

    A module which converts the UART2Register Packet to an SRAM interface

    RISCY-Lib/uart2sram’s past year of commit activity
    0 LGPL-2.1 0 0 0 Updated Apr 23, 2024
  • uvm_utils Public

    A collection of utility classes and headers for use in a UVM testbench

    RISCY-Lib/uvm_utils’s past year of commit activity
    SystemVerilog 0 LGPL-2.1 0 0 0 Updated Apr 23, 2024
  • colored_reporter Public

    A UVM Custom Report Server Implementation which uses X11 Coloring for the outputs

    RISCY-Lib/colored_reporter’s past year of commit activity
    0 GPL-3.0 0 0 0 Updated Apr 23, 2024
  • uart_agent Public

    A UART UVM Agent

    RISCY-Lib/uart_agent’s past year of commit activity
    SystemVerilog 0 LGPL-2.1 0 0 0 Updated Apr 23, 2024
  • clk_rst_agent Public

    A simple UVM Clock reset Agent

    RISCY-Lib/clk_rst_agent’s past year of commit activity
    0 GPL-3.0 0 0 0 Updated Apr 23, 2024
  • SVerilogPy Public

    A python System Verilog Parser and AST

    RISCY-Lib/SVerilogPy’s past year of commit activity
    Python 0 LGPL-2.1 0 0 0 Updated Jan 5, 2024
View all repositories

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