MIPS Base Code Refine v1 #3257
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MIPS Base Code Refine v1 #3257
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MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Previously Loongson 1B and Loongson 1C have their own libcpu implemention, but they're almost identical. So we merge them into gs232 and adapt to new common code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This bsp is used for test MIPS base code in simutator, implemented basic MIPS cpuport and serial port driver. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
LS1C selfboot feature have been rewiritten, and we changed bare boot base to 0x80000000 to better utilize memory. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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拉取/合并请求描述：(PR description)
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This is a rev of previous PR #3236 which dropped Inginic X1000 part.
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#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up