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[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs
Currently, the custom SGPR spill lowering pass spills SGPRs into physical VGPR lanes and the remaining VGPRs are used by regalloc for vector regclass allocation. This imposes many restrictions that we ended up with unsuccessful SGPR spilling when there won't be enough VGPRs and we are forced to spill the leftover into memory during PEI. The custom spill handling during PEI has many edge cases and often breaks the compiler time to time. This patch implements spilling SGPRs into virtual VGPR lanes. Since we now split the register allocation for SGPRs and VGPRs, the virtual registers introduced for the spill lanes would get allocated automatically in the subsequent regalloc invocation for VGPRs. Spill to virtual registers will always be successful, even in the high-pressure situations, and hence it avoids most of the edge cases during PEI. We are now left with only the custom SGPR spills during PEI for special registers like the frame pointer which is an unproblematic case. By spilling CSRs into virtual VGPR lanes, we might end up with broken CFIs that can potentially corrupt the frame unwinding in the debugger causing either a crash or a terrible debugging experience. This occurs when regalloc tries to spill or split the liverange of these virtual VGPRs. The CFIs should also be inserted at these intermediate points to correctly propagate the CFI entries. It is not currently implemented in the compiler. As a short-term fix, we continue to spill CSR SGPRs into physical VGPR lanes for the debugger to correctly compute the unwind information. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D124196 Change-Id: I1180639b1211b05e439132f9fc978860577c9017
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