Add a HAL implementation for SPI master

README.md

@@ -67,6 +67,7 @@ The following peripherals are supported in `avr-hal-generic`:
 - [x] A spinning delay implementation
 - [x] `PORTx` peripherals as digital IO (v2)
 - [x] A TWI based I2C implementation
+- [ ] SPI primary-mode implementation
 
 ### HAL Status
 The chip-HAL crates currently support the following peripherals:

avr-hal-generic/src/lib.rs

@@ -15,6 +15,7 @@ pub mod delay;
 pub mod port;
 pub mod serial;
 pub mod i2c;
+pub mod spi;
 
 /// Prelude containing all HAL traits
 pub mod prelude {

avr-hal-generic/src/spi.rs

@@ -0,0 +1,185 @@
+//! SPI Implementation
+
+/// Error type emitted by Spi in the event of a critical failure.  Errors have
+/// no information attached.
+#[derive(Debug, Clone, Copy)]
+pub enum SpiError {}
+
+/// Oscillator Clock Frequency division options.  Controls both SPR and SPI2X register bits.
+pub enum SerialClockRate {
+    OscfOver2,
+    OscfOver4,
+    OscfOver8,
+    OscfOver16,
+    OscfOver32,
+    OscfOver64,
+    OscfOver128,
+}
+
+/// Order of data transmission, either MSB first or LSB first
+pub enum DataOrder {
+    MostSignificantFirst,
+    LeastSignificantFirst,
+}
+
+/// Polarity of clock (whether SCLK idles at low state or high state)
+pub enum SerialClockPolarity {
+    IdleHigh,
+    IdleLow,
+}
+
+/// Clock sampling phase (check at leading or trailing edge of signal)
+pub enum SerialClockPhase {
+    SampleLeading,
+    SampleTrailing,
+}
+
+/// Implement traits for a SPI interface
+#[macro_export]
+macro_rules! impl_spi {
+    (
+        $(#[$spi_attr:meta])*
+        pub struct $Spi:ident {
+            peripheral: $SPI:ty,
+            pins: {
+                posi: $POSI:ident,
+                piso: $PISO:ident,
+            }
+        }
+    ) => {
+        type POSI = $POSI<mode::Output>;
+        type PISO = $PISO<mode::Input<mode::PullUp>>;
+
+        /// Settings to pass to Spi.
+        ///
+        /// Easiest way to initialize is with
+        /// `Settings::default()`.  Otherwise can be instantiated with alternate
+        /// settings directly.
+        pub struct Settings {
+            data_order: DataOrder,
+            clock: SerialClockRate,
+            clock_polarity: SerialClockPolarity,
+            clock_phase: SerialClockPhase,
+        }
+
+        impl Default for Settings {
+            fn default() -> Self {
+                Settings {
+                    data_order: DataOrder::MostSignificantFirst,
+                    clock: SerialClockRate::OscfOver4,
+                    clock_polarity: SerialClockPolarity::IdleLow,
+                    clock_phase: SerialClockPhase::SampleTrailing,
+                }
+            }
+        }
+
+        /// Behavior for a SPI interface.
+        ///
+        /// Stores the SPI peripheral for register access.  In addition, it takes
+        /// ownership of the POSI and PISO pins to ensure they are in the correct mode.
+        /// Instantiate with the `new` method.
+        $(#[$spi_attr])*
+        pub struct $Spi {
+            peripheral: $SPI,
+            posi: POSI,
+            piso: PISO,
+            settings: Settings,
+        }
+
+        /// Implementation-specific behavior of the struct, including setup/tear-down
+        impl $Spi {
+            /// Instantiate an SPI with the registers, POSI/PISO pins, and settings
+            pub fn new(peripheral: $SPI, posi: POSI, piso: PISO, settings: Settings) -> $Spi {
+                Spi {
+                    peripheral,
+                    posi,
+                    piso,
+                    settings,
+                }
+            }
+
+            /// Release ownership of the peripheral and pins.  Instance can no-longer
+            /// be used after this is invoked.
+            pub fn release(self) -> ($SPI, POSI, PISO) {
+                (self.peripheral, self.posi, self.piso)
+            }
+
+            /// Write a byte to the data register, which begins transmission
+            /// automatically
+            fn write(&self, byte: u8) {
+                self.peripheral.spdr.write(|w| w.bits(byte));
+            }
+
+            /// Loop forever, checking the transmission complete bit until it is set
+            fn block_until_transfer_complete(&self) {
+                while self.peripheral.spsr.read().spif().bit_is_clear() { }
+            }
+
+            /// Sets up the control/status registers with the right settings for this secondary device
+            fn setup(&self) {
+                // set up control register
+                self.peripheral.spcr.write(|w| {
+                    // enable SPI
+                    w.spe().set_bit();
+                    // Set to primary mode
+                    w.mstr().set_bit();
+                    // set up data order control bit
+                    match self.settings.data_order {
+                        DataOrder::MostSignificantFirst => w.dord().clear_bit(),
+                        DataOrder::LeastSignificantFirst => w.dord().set_bit(),
+                    };
+                    // set up polarity control bit
+                    match self.settings.clock_polarity {
+                        SerialClockPolarity::IdleHigh => w.cpol().set_bit(),
+                        SerialClockPolarity::IdleLow => w.cpol().clear_bit(),
+                    };
+                    // set up phase control bit
+                    match self.settings.clock_phase {
+                        SerialClockPhase::SampleLeading => w.cpha().clear_bit(),
+                        SerialClockPhase::SampleTrailing => w.cpha().set_bit(),
+                    };
+                    // set up clock rate control bit
+                    match self.settings.clock {
+                        SerialClockRate::OscfOver2 => w.spr().val_0x00(),
+                        SerialClockRate::OscfOver4 => w.spr().val_0x00(),
+                        SerialClockRate::OscfOver8 => w.spr().val_0x01(),
+                        SerialClockRate::OscfOver16 => w.spr().val_0x01(),
+                        SerialClockRate::OscfOver32 => w.spr().val_0x02(),
+                        SerialClockRate::OscfOver64 => w.spr().val_0x02(),
+                        SerialClockRate::OscfOver128 => w.spr().val_0x03(),
+                    }
+                });
+                // set up 2x clock rate status bit
+                self.peripheral.spsr.write(|w| match self.settings.clock {
+                    SerialClockRate::OscfOver2 => w.spi2x().set_bit(),
+                    SerialClockRate::OscfOver4 => w.spi2x().clear_bit(),
+                    SerialClockRate::OscfOver8 => w.spi2x().set_bit(),
+                    SerialClockRate::OscfOver16 => w.spi2x().clear_bit(),
+                    SerialClockRate::OscfOver32 => w.spi2x().set_bit(),
+                    SerialClockRate::OscfOver64 => w.spi2x().clear_bit(),
+                    SerialClockRate::OscfOver128 => w.spi2x().set_bit(),
+                });
+            }
+        }
+
+        /// FullDuplex trait implementation, allowing this struct to be provided to
+        /// drivers that require it for operation.  Only 8-bit word size is supported
+        /// for now.
+        impl $crate::hal::spi::FullDuplex<u8> for $Spi {
+            type Error = $crate::spi::SpiError;
+
+            /// Sets up the device for transmission and sends the data
+            fn send(&mut self, byte: u8) -> $crate::nb::Result<(), Self::Error> {
+                self.setup();
+                self.write(byte);
+                self.block_until_transfer_complete();
+                Ok(())
+            }
+
+            /// Reads and returns the response in the data register
+            fn read(&mut self) -> $crate::nb::Result<u8, Self::Error> {
+                Ok(self.peripheral.spdr.read().bits())
+            }
+        }
+    };
+}

boards/arduino-uno/examples/uno-spi-feedback.rs

@@ -0,0 +1,55 @@
+//! This example demonstrates how to set up a SPI interface and communicate over it.
+//! The physical hardware configuation consists of connecting a jumper directly from pin `~11` to
+//! pin `~12`.
+//!
+//! Once this program is written to the board, the serial output can be accessed with
+//!
+//! ```
+//! sudo screen /tty/ACM0 57600
+//! ```
+//!
+//! You should see it output the line `data: 15` repeatedly (aka 0b00001111)
+
+#![no_std]
+#![no_main]
+#![feature(proc_macro_hygiene)]
+extern crate panic_halt;
+use arduino_uno::prelude::*;
+use arduino_uno::spi::{Spi,Settings};
+#[no_mangle]
+pub extern fn main() -> ! {
+    let dp = arduino_uno::Peripherals::take().unwrap();
+    let mut delay = arduino_uno::Delay::new();
+    let mut pins = arduino_uno::Pins::new(
+        dp.PORTB,
+        dp.PORTC,
+        dp.PORTD,
+    );
+    // set up serial interface for text output
+    let mut serial = arduino_uno::Serial::new(
+        dp.USART0,
+        pins.d0,
+        pins.d1.into_output(&mut pins.ddr),
+        57600,
+    );
+
+    pins.d10.into_output(&mut pins.ddr);// SS must be set to output mode
+    // create SPI interface
+    let mut spi = Spi::new(
+        dp.SPI,
+        pins.d11.into_output(&mut pins.ddr),
+        pins.d12.into_pull_up_input(&mut pins.ddr),
+        Settings::default(),
+    );
+
+    loop {
+        // Send a byte
+        spi.send(0b00001111).unwrap();
+        // Because PISO is connected to POSI, the read data should be the same
+        let data = spi.read().unwrap();
+
+        ufmt::uwriteln!(&mut serial, "data: {}\r", data).unwrap();
+        delay.delay_ms(1000);
+    }
+}
+

boards/arduino-uno/src/lib.rs

@@ -7,6 +7,7 @@ mod pins;
 pub use atmega328p_hal::atmega328p;
 pub use crate::atmega328p::Peripherals;
 pub use atmega328p_hal::prelude;
+pub use atmega328p_hal::spi;
 pub use crate::pins::*;
 
 pub type Delay = hal::delay::Delay<hal::clock::MHz16>;

chips/atmega328p-hal/Cargo.toml

@@ -6,6 +6,11 @@ edition = "2018"
 
 [dependencies]
 avr-hal-generic = { path = "../../avr-hal-generic/" }
+nb = "0.1.2"
+
+[dependencies.embedded-hal]
+version = "0.2.3"
+features = ["unproven"]
 
 [dependencies.avr-device]
 git = "https://github.com/Rahix/avr-device"

chips/atmega328p-hal/src/lib.rs

@@ -8,6 +8,7 @@ pub use avr_hal::clock;
 pub use avr_hal::delay;
 
 pub mod port;
+pub mod spi;
 
 pub mod prelude {
     pub use crate::avr_hal::prelude::*;