September-update-1

Add custom FPGA section, 2.00 FPGA image change, XADC input range corrected

appsFeatures/command_line_tools/com_line_tool.rst

@@ -308,7 +308,7 @@ Accessing FPGA registers
 ========================
 
 Red Pitaya signal processing is based on two computational engines: the FPGA and the dual-core processor, to effectively split the tasks. Most of the high data rate signal processing is implemented within the FPGA building blocks. These blocks can be configured parametrically through registers. The FPGA registers are documented in the
-:ref:`Red Pitaya HDL memory map <fpga_094>` document. The registers can be accessed using the described monitor utility.
+:ref:`Red Pitaya HDL memory map <fpga_registers>` document (please make sure to reference the correct OS version). The registers can be accessed using the described monitor utility.
 For example, the following sequence of monitor commands checks modifies, and verifies the acquisition decimation parameter (at address 0x40100014):
 
 .. code-block:: shell-session

developerGuide/hardware/122-16_EXT/top.rst

@@ -12,7 +12,7 @@ External clock signal levels should be LVDS in the range from 1 MHz to 122.8 MHz
    The OS will not boot without providing an external clock.
 
 
-.. figure:: ../125-14/Extension_connector.png
+.. figure:: ../125-14/img/Extension_connector.png
    :align: center
 
 ************************

developerGuide/hardware/125-14/cets.rst

@@ -1,18 +1,18 @@
 CB test certificate - Safety
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. figure:: SI-4208.jpg
+.. figure:: img/certificate/SI-4208.jpg
 
 CB Test certificate - EMC
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 
-.. figure:: SI-4169.jpg
+.. figure:: img/certificate/SI-4169.jpg
 
 MET Approval Letter
 ^^^^^^^^^^^^^^^^^^^
 
-.. figure:: MET_Approval_Letter_41185.jpg
+.. figure:: img/certificate/MET_Approval_Letter_41185.jpg
 
 NRTLC Certification Record
 ^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-.. figure:: NRTLC_Certification_Record.jpg
+.. figure:: img/certificate/NRTLC_Certification_Record.jpg

developerGuide/hardware/125-14/cooling.rst

@@ -10,11 +10,11 @@ Assembly
 
 #.  Attaching the fan to the heat sink using two screws as shown in the picture below. 
 
-.. image:: cooling-screwon.jpg
+.. image:: img/cooling/cooling-screwon.jpg
    :align: center
    :scale: 70 %
 
-.. figure:: cooling-topdown.jpg 
+.. figure:: img/cooling/cooling-topdown.jpg 
    :align: center
    :scale: 70 %
 
@@ -25,7 +25,7 @@ Assembly
 Measurements
 ************
 
-.. figure:: cooling-result.png
+.. figure:: img/cooling/cooling-result.png
    :align: center
 
    Temperature measured with the fan turned off and on combined with low and high CPU load.

developerGuide/hardware/125-14/extent.rst

@@ -102,7 +102,7 @@ Pin  Description            FPGA pin number FPGA pin description Voltage levels
 
 Schematics of extension connectors are shown in the picture below.
 
-.. figure:: Extension_connector.png
+.. figure:: img/Extension_connector.png
 
 **Notes:**
 
@@ -177,7 +177,7 @@ Powering Red Pitaya through extension connector
 
 The Red Pitaya can also be powered through pin 1 of the extension connector :ref:`E2 <E2>`, but in such a case, external protection must be provided by the user in order to protect the board!
 
-.. figure:: Protection.png
+.. figure:: img/Protection.png
 
 Protection circuit between +5 V that is provided over the micro USB power connector and +5 VD that is connected to pin1 of the extension connector :ref:`E2 <E2>`.
 

developerGuide/hardware/125-14/fastIO.rst

@@ -54,12 +54,12 @@ Jumpers
 
 Voltage ranges are set by input jumpers, as shown here:
 
-.. figure:: Jumper_settings.png 
+.. figure:: img/jumpers/Jumper_settings.png 
 
 
 Gain can be adjusted independently for both input channels. The adjustment is done by bridging the jumpers located behind the corresponding input SMA connector.
 
-.. figure:: Jumper_settings_photo.png
+.. figure:: img/jumpers/Jumper_settings_photo.png
 
     Jumper setting
 
@@ -80,34 +80,38 @@ Jumper position can affect the measurements taken with Red Pitaya. The jumpers a
 
 1) The position of the jumper bumps must be as indicated in this image.
 
-    .. figure:: Jumper_position_Note.png
+    .. figure:: img/jumpers/Jumper_position_Note.png
 
 
 2) The metallic part of the jumper should look toward the PCB so that it is not visible once the jumpers are installed. Here is an example on the STEMlab 125-14 4-Input:
 
-    .. figure:: Jumper_position_4IN_0.png
+    .. figure:: img/jumpers/Jumper_position_4IN_0.png
+        :align: center
+        :width: 700 px
 
-    .. figure:: Jumper_position_4IN_1.png
+    .. figure:: img/jumpers/Jumper_position_4IN_1.png
+        :align: center
+        :width: 700 px
 
 
 Incorrect placement of the jumpers can cause overshooting or undercutting of the front part of the acquired square-type signals, as shown in the picture below.
 
-.. figure:: Jumper_position_wrong_signal.jpg
+.. figure:: img/jumpers/Jumper_position_wrong_signal.jpg
 
     As it can be observed, **if the jumpers are not placed correctly, the step response becomes under-compensated.**
 
 
 With the correct placement of the jumper pins, that same waveform looks much better.
 
-.. figure:: Jumper_position_right_signal.jpg
+.. figure:: img/jumpers/Jumper_position_right_signal.jpg
 
 
 
 ======================
 Input stage schematics
 ======================
 
-.. figure:: Fast_analog_inputs_sch.png
+.. figure:: img/Fast_analog_inputs_sch.png
 
     Fast analog inputs schematics
 
@@ -117,7 +121,7 @@ Coupling
 
 Fast analog inputs are **DC coupled**. Input impedance is given in the picture below. 
 
-.. figure:: Input_impedance_of_fast_analog_inputs.png
+.. figure:: img/measurements/Input_impedance_of_fast_analog_inputs.png
 
     The input impedance of fast analog inputs
 
@@ -131,7 +135,7 @@ Bandwidth
 
 In the picture below, the Frequency Response - Bandwidth of fast analog inputs is shown. Measurements are taken using an |Agilent 33250A| signal generator as a reference. The measured signal is acquired using :ref:`remote control (SCPI commands) <scpi_command_list>`. An amplitude voltage is extracted from the acquired signal and compared to the reference signal amplitude.
 
-.. figure:: Bandwidth_of_Fast_Analog_Inputs.png
+.. figure:: img/measurements/Bandwidth_of_Fast_Analog_Inputs.png
 
     The bandwidth of fast analog inputs
 
@@ -143,7 +147,7 @@ Notice: When making measurements without interpolation, you need to extract the
 
     In the picture, only 10 samples of 16k buffer are shown to represent a few periods of 40 MHz signal.
 
-.. figure:: Sin(x)x_Interpolation.png   
+.. figure:: img/measurements/Sin(x)x_Interpolation.png   
 
     Sin(x)/x Interpolation
 
@@ -153,11 +157,11 @@ Input noise
 
 Measurements refer to a high gain (LV +/-1 V) jumper setting, with limited environmental noise, inputs and outputs terminated, output signals disabled, and the PCB grounded through SMA ground. Measurements are performed on 16k continuous samples at full rate (125 MS/s). (Typical full bandwidth std(Vn) < 0.5 mV). The noise spectrum shown in the picture below (right) is calculated using FFT analysis on N = 16384 samples sampled at Fs = 125E6 MS/s.
 
-.. figure:: Noise_distribution.png
+.. figure:: img/measurements/Noise_distribution.png
 
     Noise distribution 
 
-.. figure:: Noise_level.png
+.. figure:: img/measurements/Noise_level.png
 
     Noise level
 
@@ -196,7 +200,7 @@ Measurements refer to the LV jumper setting, inputs, and outputs terminated, out
 
 Measurements refer to the LV jumper setting, inputs, and outputs terminated, outputs signal disabled, and the PCB grounded through SMA ground.
 
-.. figure:: Measurement_setup.png
+.. figure:: img/measurements/Measurement_setup.png
 
     Measurement setup
 
@@ -206,55 +210,55 @@ Reference signals
 
     #. Reference signal: -20 dBm, 2 MHz
 
-       .. figure:: -20dBm_2MHz_RP_AG.png
+       .. figure:: img/measurements/-20dBm_2MHz_RP_AG.png
 
             Reference Signal: -20 dBm 2 MHz
 
     #. Reference signal: -20 dBm, 10 MHz
 
-       .. figure::   -20dBm_10MHz_RP_AG.png
+       .. figure::   img/measurements/-20dBm_10MHz_RP_AG.png
 
             Reference Signal: -20 dBm 10 MHz
 
     #. Reference signal: -20 dBm, 30 MHz
 
-       .. figure:: -20dBm_30MHz_RP_AG.png
+       .. figure:: img/measurements/-20dBm_30MHz_RP_AG.png
 
             Reference Signal: -20 dBm 30 MHz
 
     #. Reference signal: 0  dBm, 2 MHz
 
-       .. figure:: 0dBm_2MHz_RP_AG.png
+       .. figure:: img/measurements/0dBm_2MHz_RP_AG.png
 
             Reference Signal: 0 dBm 2 MHz
 
     #. Reference signal: 0 dBm, 10 MHz
 
-       .. figure:: 0dBm_10MHz_RP_AG.png
+       .. figure:: img/measurements/0dBm_10MHz_RP_AG.png
 
             Reference Signal: 0 dBm 10 MHz
 
     #. Reference signal: 0 dBm, 30 MHz
 
-       .. figure:: 0dBm_30MHz_RP_AG.png
+       .. figure:: img/measurements/0dBm_30MHz_RP_AG.png
 
             Reference Signal: 0 dBm 30 MHz
 
     #. Reference signal: -3 dBFS, 2 MHz
 
-       .. figure:: -3dBFS_2MHZ_RP_AG.png
+       .. figure:: img/measurements/-3dBFS_2MHZ_RP_AG.png
 
             Reference Signal: -3 dBFS 2 MHz
 
     #. Reference signal: -3 dBFS, 10 MHz
 
-       .. figure:: -3dBFS_10MHZ_RP_AG.png
+       .. figure:: img/measurements/-3dBFS_10MHZ_RP_AG.png
 
             Reference Signal: -3 dBFS 10 MHz
 
     #. Reference signal: -3 dBFS, 30 MHz
 
-       .. figure:: -3dBFS_30MHZ_RP_AG.png
+       .. figure:: img/measurements/-3dBFS_30MHZ_RP_AG.png
 
           Reference Signal: -3 dBFS 30 MHz
 
@@ -371,7 +375,7 @@ DC OFFSET @ 122 kS/s        HV              ± 5 mV
 
 AC gain accuracy can be extracted from Frequency response - Bandwidth.
 
-.. figure:: 800px-Bandwidth_of_Fast_Analog_Inputs.png
+.. figure:: img/measurements/800px-Bandwidth_of_Fast_Analog_Inputs.png
 
 
 ##############
@@ -417,13 +421,13 @@ General Specifications
 
     The SMA connectors on the cables connected to Red Pitaya must correspond to the standard MIL­C­39012. The central pin must be of a suitable length, otherwise, the SMA connector, installed on the Red Pitaya, will mechanically damage the SMA connector. The central pin of the SMA connector on the Red Pitaya will lose contact with the board and the board will not be possible to repair due to the mechanical damage (separation of the pad from the board).
 
-.. figure:: Outputs.png
+.. figure:: img/Outputs.png
 
     Output channel Output voltage range: ± 1 V
 
 The output stage is shown in the picture below.
 
-.. figure:: Outputs_stage.png
+.. figure:: img/Outputs_stage.png
 
     Output channel schematics
 
@@ -433,7 +437,7 @@ Output impedance
 
 The impedance of the output channels (output amplifier and filter) is shown in the figure below.
 
-.. figure:: Output_impedance.png
+.. figure:: img/measurements/Output_impedance.png
 
     Output impedance
 
@@ -447,7 +451,7 @@ Bandwidth
 
 Bandwidth measurements are shown in the picture below. Measurements are taken with the |Agilent MSO7104B| oscilloscope for each frequency step (10 Hz – 60 MHz) of the measured signal. The Red Pitaya board OUT1 is used with 0 dBm output power. The second output channel and both input channels are terminated with 50 Ohm termination. The Oscilloscope ground is used to ground the Red Pitaya board. The oscilloscope input must be set to 50 Ohm input impedance.
 
-.. figure:: Fast_Analog_Outputs_Bandwidt.png
+.. figure:: img/measurements/Fast_Analog_Outputs_Bandwidt.png
 
 
 =========

developerGuide/hardware/125-14/top.rst

@@ -149,6 +149,8 @@ Technical specifications
 
     For more information, please refer to the :ref:`Product comparison table <rp-board-comp>`.
 
+.. _schematics_125_14:
+
 **********
 Schematics
 **********
@@ -211,12 +213,12 @@ External ADC clock
 
 The ADC clock can be provided by:
 
-    * On board 125 MHz XO (default)
-    * From an external source/through extension connector :ref:`E2 <E2>` (R25, R26 should be moved to location R23, R24)
-    * Directly from the FPGA (R25, R26 should be relocated to R27, R28) 
+    - On board 125 MHz XO (default)
+    - From an external source/through extension connector :ref:`E2 <E2>` (R25, R26 should be moved to location R23, R24)
+    - Directly from the FPGA (R25, R26 should be relocated to R27, R28) 
 
-.. figure:: External_clk.png
-    :alt: Logo
+.. figure:: img/External_clk.png
+    :alt: Schematic
     :align: center
 
     Schematic
@@ -227,24 +229,31 @@ The ADC clock can be provided by:
     We do not advise altering the board because users have reported problems after doing so. Every board made has undergone rigorous testing, which cannot be claimed for modified boards. Any non-Red Pitaya hardware modification will void the warranty, and we cannot guarantee support for modified boards.
 
 
-.. figure:: External_clock_top.png
-    :alt: Logo
+.. figure:: img/External_clock_top.png
+    :alt: Top side schematic
     :align: center
 
-    Top side
+    Top side schematic
 
 
-.. figure:: External_clock_bottom.png
-    :alt: Logo
+.. figure:: img/External_clock_bottom.png
+    :alt: Bottom side schematic
     :align: center
 
-    Bottom side
+    Bottom side schematic
 
-.. figure:: External_clock_bottom_photo.png
-    :alt: Logo
+.. figure:: img/External_clock_bottom_photo.png
+    :alt: Bottom side photo
     :align: center
     :width:  400px
 
+    Bottom side photo
+
+.. figure:: img/External_clock_resistors.jpeg
+    :alt: Bottom side all
+    :align: center
+
+    Bottom side
 
 ************
 Certificates
@@ -269,7 +278,7 @@ Cooling options
 
 For additional cooling, we recommend a 30 mm or 25 mm fan. You can use the board's power connector to power the fan, but please note that it supplies only 5 V. The power connector is located between the micro-SD socket and the host USB connector.
 
-.. figure:: cooling-powerPin.jpg
+.. figure:: img/cooling/cooling-powerPin.jpg
     :width: 50%
     :align: center
 

developerGuide/hardware/125-14_EXT/top.rst

@@ -9,7 +9,7 @@ This STEMlab version is standard STEMlab 125-14 modified in such a way that the
 
    The OS will not boot without providing an external clock.
 
-.. figure:: ../125-14/Extension_connector.png
+.. figure:: ../125-14/img/Extension_connector.png
    :align: center