FPGA-docs-fix

Fpga docs

developerGuide/software/build/comC.rst

@@ -10,9 +10,14 @@ acquisition, digital I/O control, communication: I2C, SPI, UART and other).
 How to compile a C algorithm is shown in the instructions below, while a list of Examples is available
 :ref:`here <list-of-supported-scpi-commands>`.
 
-Note: When you copy the source code from our repository (following instructions bellow) you will also
-copy all C examples to your Red Pitaya board. After that only the compiling step is needed.
+.. note::
 
+    When you copy the source code from our repository (following instructions below) you will also copy all C examples to your Red Pitaya board. After that only the compiling step is needed.
+
+.. note::
+
+    Here is a :ref:`link to the rp.c <https://github.com/RedPitaya/RedPitaya/blob/master/rp-api/api/src/rp.c>` which contains all the C functions used in the examples.
+
 
 **Compiling and running on Red Pitaya board**
 
@@ -24,6 +29,12 @@ First connect to your board over :ref:`SSH <ssh>` (replace the IP, the default p
 
     ssh root@192.168.0.100
 
+You can also use the .local address (not all computers support .local addresses) (replace 'xxxxxx' with the last 6 characters of the Red Pitaya's MAC address):
+
+.. code-block:: shell-session
+
+    ssh root@rp-xxxxxx.local
+
 Now make a clone of the Red Pitaya Git repository and enter the project directory.
 
 .. code-block:: shell-session

developerGuide/software/build/fpga/fpga.rst

@@ -39,6 +39,7 @@ Install libraries:
 
    # apt-get install unixodbc unixodbc-dev libncurses-dev libzmq3-dev libxext6 libasound2 libxml2 libx11-6 libxtst6 libedit-dev libxft-dev libxi6 libx11-6:i386 libxau6:i386 libxdmcp6:i386 libxext6:i386 libxft-dev:i386 libxrender-dev:i386 libxt6:i386 libxtst6:i386
 
+
 Xilinx Vivado 2020.1
 ====================
 
@@ -66,6 +67,7 @@ For more information on Vivado installation, see:
 
 https://redpitaya-knowledge-base.readthedocs.io/en/latest/learn_fpga/3_vivado_env/tutorfpga1.html
 
+
 Xilinx SDK development environments 2019.1
 ==========================================
 
@@ -507,7 +509,6 @@ Generic device tree files can be found in ``fpga/dts`` while project specific co
 Signal mapping
 **************
 
-===========
 XADC inputs
 ===========
 
@@ -527,7 +528,7 @@ XADC input data can be accessed through the Linux IIO (Industrial IO) driver int
 |        | AIF[PN]4  | K9 /L10  | AD      | in_voltage8_vpvn_raw  | 5V power supply    | 12.2V |
 +--------+-----------+----------+---------+-----------------------+--------------------+-------+
 
------------
+
 Input range
 -----------
 
@@ -543,7 +544,7 @@ but it requires removing R273 and providing a **0.5V ~ 1V** common voltage on th
    where the XADC input range in unipolar mode was thought to be **0V ~ 0.5V**.
    Consequently the voltage dividers were miss designed for a range of double the supply voltage.
 
-~~~~~~~~~~~~~~~
+
 5V power supply
 ~~~~~~~~~~~~~~~
 
@@ -560,7 +561,7 @@ but it requires removing R273 and providing a **0.5V ~ 1V** common voltage on th
 
    range = \frac{1 V}{ratio} = 12.2 V
 
-~~~~~~~~~~~~~~~~~~~~~~
+
 General purpose inputs
 ~~~~~~~~~~~~~~~~~~~~~~
 
@@ -577,7 +578,7 @@ General purpose inputs
 
    range = \frac{1 V}{ratio} = 7.01 V
 
-=============
+
 GPIO and LEDs
 =============
 
@@ -634,7 +635,7 @@ The default pin assignment for GPIO is described in the next table.
 | ``B9`` | ``E2[10]`` | I2C0_SDA           |  ``MIO[51]``     | ``906+   [51]   = 957``      | requires ``pinctrl`` changes to be active |
 +--------+------------+--------------------+------------------+------------------------------+-------------------------------------------+
 
-===================
+
 Linux access to LED
 ===================
 
@@ -654,7 +655,7 @@ To switch LED 8 ON use:
 
    $ echo 1 > /sys/class/leds/led0/brightness
 
-==============================
+
 PS ``pinctrl`` for MIO signals
 ==============================
 

developerGuide/software/build/fpga/regset_common.rst

@@ -1,5 +1,6 @@
 .. _fpga_094:
 
+
 ********************
 Register map (v0.94)
 ********************
@@ -34,16 +35,17 @@ For additional information and better understanding check other documents (schem
 | CS[7]  | 0x40700000  | 0x407FFFFF | Power test                       |
 +--------+-------------+------------+----------------------------------+
 
-==================
+
 Red Pitaya Modules
 ==================
 
 Here are described submodules used in Red Pitaya FPGA logic.
 
-------------
+
 Housekeeping
 ------------
 
+
 .. tabs::
 
     .. group-tab:: 12X-XX
@@ -524,7 +526,7 @@ Housekeeping
         |          |  1: enable, 0: disable                         |      |     |
         +----------+------------------------------------------------+------+-----+
 
-------------
+
 Oscilloscope
 ------------
 
@@ -819,7 +821,6 @@ Oscilloscope
 +----------+----------------------------------------------------+------+-----+    
 
 
---------------------------------
 Arbitrary Signal Generator (ASG)
 --------------------------------
 
@@ -1557,7 +1558,7 @@ Arbitrary Signal Generator (ASG)
         +----------+----------------------------------------------------+------+-----+
 
 
---------------
+
 PID Controller
 --------------
 
@@ -1747,7 +1748,7 @@ Analog Mixed Signals (AMS)
 |          | Bit select for PWM repetition which have value PWM+1| 15:0 | R/W |
 +----------+-----------------------------------------------------+------+-----+    
 
------------
+
 Daisy Chain
 -----------
 
@@ -1809,7 +1810,7 @@ Daisy Chain
 |          | 0 is received                                      |      |     |
 +----------+----------------------------------------------------+------+-----+    
 
-----------
+
 Power Test
 ----------
 

developerGuide/software/other_info/spi/spi.rst

@@ -2,20 +2,20 @@
 SPI interface
 #########################
 
-SPI interface support to the :ref:`E2 <E2>` connector, without the need for specific FPGA code.
+SPI interface support for the :ref:`E2 <E2>` connector without the need for a specific FPGA code.
 
-By default on all RedPitaya boards, the CS state of the SPI is set to HIGH (inactive).
+By default, on all RedPitaya boards, the CS state of the SPI is set to HIGH (inactive).
 
-If you want to set the default value to LOW (inactive), then you need to rebuild the device tree. This can be done on redpitai itself.
-First you need to open the file using a command in the console with a description of the device tree..
+If you want to set the default value to LOW (inactive), then you need to rebuild the device tree. This can be done on the Red Pitaya itself.
+First, you need to open the file using a command in the console with a description of the device tree.
 
 .. code-block:: console
 
    root@rp-f01c3d:~# rw
    root@rp-f01c3d:~# nano /opt/redpitaya/dts/$(monitor -f)/dtraw.dts
 
 
-In the file you need to find the SPI device: spidev@0
+In the file, you need to find the SPI device: spidev@0
 and add the line *spi-cs-high* to this device;
 
 .. figure:: img/spi_dts.png
@@ -33,11 +33,11 @@ After that, you need to rebuild the tree and restart the board
 
 .. note::
 
-   The settings are applied only after the device tree is loaded. When the board starts up, the CS value is in the HIGH state.
+   The settings are applied only after the device tree is loaded. When the board starts up, the CS value is in the HIGH state but will change to LOW after the boot is complete.
 
 .. note::
 
-   You can also switch the driver mode through the settings. See commands from hw api:
+   You can also switch the driver mode through the settings. See commands from :ref:`hw api<scpi_command_list>`:
 
    * rp_SPI_GetCSMode
-   * rp_SPI_SetCSMode
+   * rp_SPI_SetCSMode

quickStart/SDcard/SDcard.rst

@@ -14,7 +14,7 @@ The next procedure will create a clean SD card image.
 
 RedPitaya OS 2.0:
 
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/Unify/RedPitaya_OS_2.00-15_beta.img.zip>`_  - |CHANGELOG|
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/Unify/RedPitaya_OS_2.00-15_beta.img.zip>`_  - |CHANGELOG| (MD5 (zipped): 18cb8bdc3c623f0e8de31b30316cbf10)
 
 .. note::
 
@@ -42,32 +42,32 @@ RedPitaya OS 2.0:
 
 STEMlab 125-14 & STEMlab 125-10:
 
-   - `Latest Stable <https://downloads.redpitaya.com/downloads/STEMlab-125-1x/STEMlab_125-xx_OS_1.04-18_stable.img.zip>`_  - |CHANGELOG|
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/STEMlab-125-1x/STEMlab_125-xx_OS_1.04-28_beta.img.zip>`_  - |CHANGELOG|
+   - `Latest Stable <https://downloads.redpitaya.com/downloads/STEMlab-125-1x/STEMlab_125-xx_OS_1.04-18_stable.img.zip>`_  - |CHANGELOG| (MD5 (zipped): f6cde9b3264a12372873d039535e58d5)
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/STEMlab-125-1x/STEMlab_125-xx_OS_1.04-28_beta.img.zip>`_  - |CHANGELOG| (MD5 (zipped): 92e14e68d27e63568fb87954239e9fb0)
 
 
 STEMlab 125-14 (SECONDARY/SLAVE board):
 
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/Streaming_slave_boards/STEMlab-125-1x/STEMlab_125-xx_OS_1.04-6_slave_beta.img.zip>`_  - |CHANGELOG|
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/Streaming_slave_boards/STEMlab-125-1x/STEMlab_125-xx_OS_1.04-6_slave_beta.img.zip>`_  - |CHANGELOG| (MD5 (zipped): ef928d3014d806539e4360e59b7f6a99)
 
 STEMlab 125-14-Z7020:
 
-   - `Latest Stable <https://downloads.redpitaya.com/downloads/STEMlab-125-14-Z7020/STEMlab_125-14-Z7020_OS_1.04-10_stable.img.zip>`_  - |CHANGELOG|
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/STEMlab-125-14-Z7020/STEMlab_125-14-Z7020_OS_1.04-14_beta.img.zip>`_  - |CHANGELOG|
+   - `Latest Stable <https://downloads.redpitaya.com/downloads/STEMlab-125-14-Z7020/STEMlab_125-14-Z7020_OS_1.04-10_stable.img.zip>`_  - |CHANGELOG| (MD5 (zipped): 3770f34e954674b0423db33ed8a3471d)
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/STEMlab-125-14-Z7020/STEMlab_125-14-Z7020_OS_1.04-14_beta.img.zip>`_  - |CHANGELOG| (MD5 (zipped): c740aab5d7b374924f19171e1edd3161)
 
 STEMlab 125-14 4-Input:
 
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/STEMlab-125-14-Z7020-4CH/STEMlab_125-14-4CH_OS_1.04-3_beta.img.zip>`_  - |CHANGELOG_Z20_4CH|
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/STEMlab-125-14-Z7020-4CH/STEMlab_125-14-4CH_OS_1.04-3_beta.img.zip>`_  - |CHANGELOG_Z20_4CH| (MD5 (zipped): 414c1e7572ec116657a356f3ee2000ac)
 
 SDRlab 122-16:
 
-   - `Latest Stable <https://downloads.redpitaya.com/downloads/SDRlab-122-16/SDRlab_122-16_OS_1.04-11_stable.img.zip>`_  - |CHANGELOG_Z20|
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/SDRlab-122-16/SDRlab_122-16_OS_1.04-15_beta.img.zip>`_  - |CHANGELOG_Z20|
+   - `Latest Stable <https://downloads.redpitaya.com/downloads/SDRlab-122-16/SDRlab_122-16_OS_1.04-11_stable.img.zip>`_  - |CHANGELOG_Z20| (MD5 (zipped): 634cf27555d4ae8900c92833afc1ddb9)
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/SDRlab-122-16/SDRlab_122-16_OS_1.04-15_beta.img.zip>`_  - |CHANGELOG_Z20| (MD5 (zipped): ba9f8be2f19630b42ee7b56bdd1d4392)
 
 SIGNALlab 250-12:
 
-   - `Latest Stable <https://downloads.redpitaya.com/downloads/SIGNALlab-250-12/SIGNALlab_250-12_OS_1.04-27_stable.img.zip>`_  - |CHANGELOG_Z20_250_12|
-   - `Latest Beta <https://downloads.redpitaya.com/downloads/SIGNALlab-250-12/SIGNALlab_250-12_OS_1.04-30_beta.img.zip>`_  - |CHANGELOG_Z20_250_12|
+   - `Latest Stable <https://downloads.redpitaya.com/downloads/SIGNALlab-250-12/SIGNALlab_250-12_OS_1.04-27_stable.img.zip>`_  - |CHANGELOG_Z20_250_12| (MD5 (zipped): 40601a42fb06cf23f43aefe15d042a01)
+   - `Latest Beta <https://downloads.redpitaya.com/downloads/SIGNALlab-250-12/SIGNALlab_250-12_OS_1.04-30_beta.img.zip>`_  - |CHANGELOG_Z20_250_12| (MD5 (zipped): 2acb0579dbf67a40828a9b60a59be9e8)
 
 
 .. |CHANGELOG| raw:: html