Merge pull request #34 from Lightsaver7/FPGA-update

Fpga update

learn_fpga/3_vivado_env/tutorfpga1.rst

@@ -1,3 +1,5 @@
+.. _install_Vivado:
+
 ######################
 Installation of Vivado
 ######################

learn_fpga/3_vivado_env/tutorfpga2.rst

@@ -34,7 +34,8 @@ Alternatively, if you are using Linux or WSL, you can first install git, then mo
 Make an FPGA project
 *******************
 
-Go to the downloaded ZIP location and extract it. You will enter the FPGA folder and make a Vivado project. Open a terminal and input the following commands.
+Go to the downloaded ZIP location and extract it.
+Now open Vivado and using the TCL console navigate to the extracted folder and make a Vivado project.
 
 .. code-block:: bash
 
@@ -45,7 +46,7 @@ Go to the downloaded ZIP location and extract it. You will enter the FPGA folder
 
 .. note::
 
-    In order to open a project for models SDRlab 122-16 or SIGNALlab 250-12, you need to specify MODEL=Z20 or MODEL=Z20_250 as a parameter.
+    In order to open a project for models SDRlab 122-16 or SIGNALlab 250-12, you need to specify MODEL=Z20 (SDRlab) or MODEL=Z20_250 (SIGNALlab) as a parameter.
 
 
 .. figure:: ./../img/Screen9.png
@@ -84,7 +85,7 @@ Finally, insert this code at the end of the module, before **endmodule: red_pita
     :width: 50%
     :align: center
 
-Now you have to start synthesis, implementation, and writing a bitstream. Press the button to start the synthesis.
+Now you have to start synthesis, implementation, and writing a bitstream. Press the button to start the synthesis. You can also just click on the "Generate bitstream" and all the steps will execute automatically.
 
 .. figure:: ./../img/sith.png
     :width: 50%
@@ -111,7 +112,7 @@ You have to send this file to your Red Pitaya board. Open a terminal and connect
     ssh root@your Red Pitaya IP
     redpitaya> rw
 
-Open another Terminal and go to the .bit file location.
+Open Terminal and go to the .bit file location.
 
 .. code-block:: bash
     
@@ -123,7 +124,7 @@ Send the file .bit to the Red Pitaya with ``scp`` command.
     
     scp red_pitaya_top.bit root@your Red Pitaya IP:/tmp
 
-Go back to the Red Pitaya Terminal and check if you have the copy **red_pitaya_top.bit**
+Now establish an `SSH communication<https://redpitaya.readthedocs.io/en/latest/developerGuide/software/console/ssh/ssh.html#establish-remote-ssh-connection>`_ with your Red Pitaya check if you have the copy **red_pitaya_top.bit** in the tmp directory.
 
 .. code-block:: bash
 

learn_fpga/4_lessons/FreqCounter.rst

@@ -40,9 +40,19 @@ To program the FPGA simply execute the following line in the Linux console on yo
 
 If you want to roll back to the official Red Pitaya FPGA program, run the following command:
 
-.. code-block:: shell-session
+.. tabs::
+
+    .. group-tab:: OS version 1.04 or older
+
+        .. code-block:: shell-session
+
+            redpitaya> cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg
+
+    .. group-tab:: OS version 2.00
+
+        .. code-block:: shell-session
 
-    cat /opt/redpitaya/fpga/fpga_X.XX.bit > /dev/xdevcfg
+            redpitaya> overlay.sh v0.94
 
 or simply restart your  Red Pitaya.
 

learn_fpga/4_lessons/KnightRider.rst

@@ -38,9 +38,19 @@ To program the FPGA simply execute the following line in the Linux console on yo
 
 Now, you should see an LED blink. Don’t worry, you did not destroy your Red Pitaya. If you want to roll back to the official Red Pitaya FPGA program, run the following command:
 
-.. code-block:: shell-session
+.. tabs::
+
+    .. group-tab:: OS version 1.04 or older
+
+        .. code-block:: shell-session
+
+            redpitaya> cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg
 
-    cat /opt/redpitaya/fpga/fpga_X.XX.bit > /dev/xdevcfg
+    .. group-tab:: OS version 2.00
+
+        .. code-block:: shell-session
+
+            redpitaya> overlay.sh v0.94
 
 or simply restart your Red Pitaya.
 
@@ -50,15 +60,11 @@ Introduction
 ============
 
 A blinking LED is one thing, but a true light show is something one can actually be proud of.
-In the |LED blink|, we built a very simple FPGA program that made one LED on the Red Pitaya blink.
+In the :ref:`LED blink example <ledblink>`, we built a very simple FPGA program that made one LED on the Red Pitaya blink.
 For such a simple project, we constructed the necessary logic by graphically connecting different blocks in *Vivado’s IP Integrator* without writing a single line of code.
 Of course, not all applications will be so simple and we will eventually have to learn hardware definition language (HDL). 
 To get acquainted with Verilog HDL, we will in this project build an FPGA program for Red Pitaya where eight lights slide like in the cult series, The Knight Rider.
 
-.. |LED blink| raw:: html
-
-   <a href="https://redpitaya-knowledge-base.readthedocs.io/en/latest/learn_fpga/4_lessons/LedBlink.html#simple-led-blinker" target="_blank">LED blink example</a>
-
 .. raw:: html
 
     <div style="position: relative; padding-bottom: 30.25%; overflow: hidden; max-width: 50%; margin-left:auto; margin-right:auto;">

learn_fpga/4_lessons/LedBlink.rst

@@ -46,9 +46,19 @@ To program the FPGA simply execute the following line in the Linux console on yo
 
 Now, you should see an LED blink. Don’t worry, you did not destroy your Red Pitaya. If you want to roll back to the official Red Pitaya FPGA program, run the following command:
 
-.. code-block:: shell-session
+.. tabs::
+
+    .. group-tab:: OS version 1.04 or older
+
+        .. code-block:: shell-session
+
+            redpitaya> cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg
+
+    .. group-tab:: OS version 2.00
+
+        .. code-block:: shell-session
 
-    cat /opt/redpitaya/fpga/fpga_X.XX.bit > /dev/xdevcfg
+            redpitaya> overlay.sh v0.94
 
 or simply restart your Red Pitaya.
 

learn_fpga/4_lessons/PingPong.rst

@@ -11,9 +11,9 @@ This is a continuation of the project → :ref:`vga image <vga_image>`
 Building the Project
 ====================
 
-Move to folder *RedPitaya/fpga/prj/Examples*. 
+Move to folder *RedPitaya-FPGA/prj/Examples*. 
 Uncomment the line "set project_name Vga_game" and comment all files in the make_project.tcl file. 
-Open Vivado and in Vivado Tcl Console navigate to the base folder: *RedPitaya/fpga/prj/Examples*. 
+Open Vivado and in Vivado Tcl Console navigate to the base folder: *RedPitaya-FPGA/prj/Examples*. 
 
 .. figure:: img/VgaImage2.png
     :alt: Logo
@@ -81,7 +81,7 @@ Ok, let's explain block diagram:
 #. The last important IP is Clocking Wizard (*clk_wiz_0*). Linux sets the clock on the FCLK_CLK0 port to 125 MHz, but we need a 50 MHz clock so we place a Clocking Wizard in order to lower the clock frequency to the desired rate.
 
 
-Picture IP and VGA IP are located in *RedPitaya/fpga/prj/Examples/Vga_draw*
+Picture IP and VGA IP are located in *RedPitaya-FPGA/prj/Examples/Vga_draw*
 
 Setting 50 MHz clock
 ***********************
@@ -169,7 +169,7 @@ Press next and set the project name (Ping_pong). Leave the rest of the parameter
 When prompted to choose a domain template, check if it matches the created platform and click next.
 The next step is choosing a template - I have chosen an *Empty Linux Application*.
 
-Next we need to copy the main.c file from Vga_draw into our application project - in the Explorer sub-window right click on the project and select *Import Sources...*, navigate to *RedPitaya/fpga/prj/Examples/Vga_draw/Vitis_sources* and click OK. Then check the *main.c* file and click *Finish*.
+Next we need to copy the main.c file from Vga_draw into our application project - in the Explorer sub-window right click on the project and select *Import Sources...*, navigate to *RedPitaya-FPGA/prj/Examples/Vga_draw/Vitis_sources* and click OK. Then check the *main.c* file and click *Finish*.
 
 The main.c file should now be visible in the *src* folder of the Explorer sub-window.
 
@@ -593,7 +593,7 @@ Setting up addressing:
 Writing game code in C++
 ************************
 
-The complete game code is located in *RedPitaya/fpga/prj/Examples/Vga_game/Vitis_sources*. In the following chapters we will discuss what the important parts of the code do.
+The complete game code is located in *RedPitaya-FPGA/prj/Examples/Vga_game/Vitis_sources*. In the following chapters we will discuss what the important parts of the code do.
 
 All classes Rectangle, Keyboard, Ball - describe work with the corresponding IP cores, constructors take a file descriptor as input, and an address in memory for the corresponding IP cores.
 

learn_fpga/4_lessons/StopWatch.rst

@@ -40,9 +40,19 @@ To program the FPGA simply execute the following line in the Linux console on yo
 
 If you want to roll back to the official Red Pitaya FPGA program, run the following command:
 
-.. code-block:: shell-session
+.. tabs::
+
+    .. group-tab:: OS version 1.04 or older
+
+        .. code-block:: shell-session
+
+            redpitaya> cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg
+
+    .. group-tab:: OS version 2.00
+
+        .. code-block:: shell-session
 
-    cat /opt/redpitaya/fpga/fpga_X.XX.bit > /dev/xdevcfg
+            redpitaya> overlay.sh v0.94
 
 or simply restart your Red Pitaya.
 

learn_fpga/4_lessons/VgaImage.rst

@@ -23,9 +23,9 @@ Required hardware:
 Building the Project
 ====================
 
-Move to folder RedPitaya/fpga/prj/Examples. 
+Move to folder RedPitaya-FPGA/prj/Examples. 
 Uncomment the line "set project_name Vga_image" and comment all files in the make_project.tcl file.
-Open Vivado and in Vivado Tcl Console navigate to the base folder: RedPitaya/fpga/prj/Examples.
+Open Vivado and in Vivado Tcl Console navigate to the base folder: RedPitaya-FPGA/prj/Examples.
 
 .. figure:: img/VgaImage2.png
     :alt: Logo

learn_fpga/4_lessons/top.rst

@@ -38,11 +38,7 @@ At this point, it is assumed that your Red Pitaya has successfully connected to
 
 For the FPGA development platform, we will use Xilinx’s Vivado Design Suite with SDK. At the time of writing, the latest version was Vivado 2020.1. However, other versions would also work. The Vivado Suite can be installed for free with a WebPACK licence, which can be downloaded after registration from their webpage.
 
-To install Vivado, please use the |Vivado installation guide|.
-
-.. |Vivado installation guide| raw:: html
-
-    <a href="https://redpitaya-knowledge-base.readthedocs.io/en/latest/learn_fpga/3_vivado_env/tutorfpga1.html#installation-of-vivado" target="_blank">Vivado installation guide</a>
+To install Vivado, please use the :ref:`Vivado installation guide <install_Vivado>`.
 
 If you are planning on developing or changing the ecosystem, you can instead install the Vitis platform (which includes Vivado and SDK, version 2020.1 or higher).
 

learn_fpga/advanced.rst

@@ -140,9 +140,7 @@ More details can be found `here <https://www.koheron.com/blog/2016/09/27/pulse-d
 Synchronize a cluster of Red Pitayas
 =====================================
 
-In its standard configuration, the Red Pitaya uses an on-board 125 MHz crystal to feed the 125 MSPS ADC and the 125 
-MSPS DAC. This example shows how to synchronize multiple Red Pitayas on the same clock using the SATA connector
-(daisy-chain) available on the Red Pitaya.
+In its standard configuration, the Red Pitaya uses an on-board 125 MHz crystal to feed the 125 MSPS ADC and the 125  MSPS DAC. This example shows how to synchronize multiple Red Pitayas on the same clock using the SATA connector (daisy-chain) available on the Red Pitaya.
 
 More details can be found `here <https://www.koheron.com/blog/2016/11/29/red-pitaya-cluster.html>`__.