This repository represents the CMOS implementation of a Comparator circuit with an RS Latch. The circuit was built using Synopsys Custom Compiler tool on a 28nm Technology.
Comparators form the basic building blocks in various circuits such as ADCs. The scope of this project is to design a comparator with an output SR Latch to latch the outputs obtained to fixed values. A comparator senses a differential input and generates a logical output according to the polarity of the input difference. Here, a Strong Arm Latch has been selected as the comparator core. This topology offers desirable attributes like operating in a single clock phase, drawing zero static power. The circuit was implemented using Synopsys 28nm PDK.
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Synopsys Custom Compiler was used to draw the transistor level schematic diagram of the design.
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Synopsys PrimeSim was used to plot the resultant transient analysis waveforms.
Most of the design effort is expended on selecting the transistor dimensions. A width dimension of 0.5um was used for clocked transistors S1-4. Transistors M1-4 were given a width of 10um, M5-6 2.5um and M7 2um.
Fig 1: Schematic of Comparator
The pmos of inverters were sized double the nmos, 0.4um and 0.2um respectively. All the pmos in the SR Latch circuit were built at 0.4um width.
Fig 2: Schematic of SR Latch
When CK is enabled, the nodes P, Q, X, and Y gets charged to VDD. We denote the capacitances at these nodes by CP, CQ, CX, and CY, respectively, and assume that CP = CQ and CX = CY. When CK goes high, M1 and M2 act as a differential pair with capacitive loads, and VP and VQ fall from VDD while yielding a differential component proportional to Vin1 - Vin2. This mode continues until VP and VQ drop to roughly VDD - VTH3,4. At the end of this mode, M3 and M4 turn on, causing VX and VY to fall until M5 and M6 are activated. One output is then pulled back to VDD by M5 or M6 while the other falls to zero. The role of M3 and M4 is to cut the current path from VDD to the ground after the comparator has made a decision. In the precharge mode, that is when the clock is low, the Strong-Arm comparator’s decision is erased, and the outputs do not represent a valid logical level, potentially confusing the following stages. To resolve this issue, a reset-set (RS) latch is inserted in the output path. As illustrated in Figure 2, the RS latch can change its state only when VX or VY falls to zero. This latch then retains the state as the Strong Arm circuit enters the precharge mode.
A pulse wave of 1GHz was set as the circuit clock. The circuit Vdd was given as 1.05V. A constant voltage of 0.5V was supplied at input terminal 2. A voltage varying between 0.45 and 0.55 was sourced in terminal 1. X and Y plot represents the unlatched outputs of the circuit. A and B is Q and Q! of the latched output.
Fig 3: SR latch truth table
When input1 < input2 , comparator output is 0, which is inverted to high, to be the set input of SR Latch, thus getting a high output at A terminal. And when input1 > input2, comparator outputs 1, which is inverted to low, which reaches the set input of SR latch. This generates a low output at the output terminal A. The above truth table supports the obtained result.
Fig 4: Simulation Wave forms
1. Delay: Delay of the circuit is obtained as 0.2 ns. It is clear from the comparison between waveforms CLK high and output A switch.
Fig 5: Delay of circuit
2. Offset Voltage There was no offset voltage observed. Similiar inputs were given on both the input terminals and the output was observed. There were no significant voltages variations observed at the output.
Attaching is the final netlist of the design here: netlist.txt
I express my special thanks to Kunal Ghosh, the Co-Founder of VLSI System Design, Corp. Pvt. Ltd. for coordinating this event and making it a grand success. I have acheived a great amount of knowledge by participating in this event. Thank you Chinmay panda and Sameer Durgoji for the quick guidance and support. I would also like to extend my sincere gratitude to Synopsys India, for making this event possible. Lastly, thanking IIT Hyderabad for this oppurtunity.
[1] B. Razavi, "The StrongARM Latch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 12-17, Spring 2015, doi: 10.1109/MSSC.2015.2418155.H. Simpson, Dumb Robots, 3rd ed., Springfield: UOS Press, 2004, pp.6-9.
[2] B. Razavi, "The Design of a Comparator [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 12, no. 4, pp. 8-14, Fall 2020, doi: 10.1109/MSSC.2020.3021865.