A project to test if a proposition is a tautology (always true, regardless of parameters) on an FPGA. This is not a SAT solver.
This projects consists of two parts: a tautology-checker written in Verilog that runs on the FPGA and a codegenerator that converts the proposition into Verilog code.
- Parallel checking in FPGA
- Support for multiple FPGA's
- Compare languages (Python, C, Verilog, GPU?)