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…icetree-rebasing.git/commit/?id=4308f0f347c4265eb98e689d8cde13795156d3ea Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
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Conexant Digicolor Platforms Device Tree Bindings | ||
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Each device tree must specify which Conexant Digicolor SoC it uses. | ||
Must be the following compatible string: | ||
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cnxt,cx92755 |
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* QEMU Firmware Configuration bindings for ARM | ||
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QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets | ||
provide the following Firmware Configuration interface on the "virt" machine | ||
type: | ||
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- A write-only, 16-bit wide selector (or control) register, | ||
- a read-write, 64-bit wide data register. | ||
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QEMU exposes the control and data register to ARM guests as memory mapped | ||
registers; their location is communicated to the guest's UEFI firmware in the | ||
DTB that QEMU places at the bottom of the guest's DRAM. | ||
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||
The guest writes a selector value (a key) to the selector register, and then | ||
can read the corresponding data (produced by QEMU) via the data register. If | ||
the selected entry is writable, the guest can rewrite it through the data | ||
register. | ||
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The selector register takes keys in big endian byte order. | ||
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The data register allows accesses with 8, 16, 32 and 64-bit width (only at | ||
offset 0 of the register). Accesses larger than a byte are interpreted as | ||
arrays, bundled together only for better performance. The bytes constituting | ||
such a word, in increasing address order, correspond to the bytes that would | ||
have been transferred by byte-wide accesses in chronological order. | ||
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The interface allows guest firmware to download various parameters and blobs | ||
that affect how the firmware works and what tables it installs for the guest | ||
OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel and | ||
initrd images for direct kernel booting, virtual machine UUID, SMP information, | ||
virtual NUMA topology, and so on. | ||
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The authoritative registry of the valid selector values and their meanings is | ||
the QEMU source code; the structure of the data blobs corresponding to the | ||
individual key values is also defined in the QEMU source code. | ||
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The presence of the registers can be verified by selecting the "signature" blob | ||
with key 0x0000, and reading four bytes from the data register. The returned | ||
signature is "QEMU". | ||
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The outermost protocol (involving the write / read sequences of the control and | ||
data registers) is expected to be versioned, and/or described by feature bits. | ||
The interface revision / feature bitmap can be retrieved with key 0x0001. The | ||
blob to be read from the data register has size 4, and it is to be interpreted | ||
as a uint32_t value in little endian byte order. The current value | ||
(corresponding to the above outer protocol) is zero. | ||
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The guest kernel is not expected to use these registers (although it is | ||
certainly allowed to); the device tree bindings are documented here because | ||
this is where device tree bindings reside in general. | ||
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Required properties: | ||
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- compatible: "qemu,fw-cfg-mmio". | ||
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- reg: the MMIO region used by the device. | ||
* Bytes 0x0 to 0x7 cover the data register. | ||
* Bytes 0x8 to 0x9 cover the selector register. | ||
* Further registers may be appended to the region in case of future interface | ||
revisions / feature bits. | ||
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Example: | ||
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/ { | ||
#size-cells = <0x2>; | ||
#address-cells = <0x2>; | ||
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fw-cfg@9020000 { | ||
compatible = "qemu,fw-cfg-mmio"; | ||
reg = <0x0 0x9020000 0x0 0xa>; | ||
}; | ||
}; |
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Rockchip SRAM for pmu: | ||
------------------------------ | ||
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The sram of pmu is used to store the function of resume from maskrom(the 1st | ||
level loader). This is a common use of the "pmu-sram" because it keeps power | ||
even in low power states in the system. | ||
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Required node properties: | ||
- compatible : should be "rockchip,rk3288-pmu-sram" | ||
- reg : physical base address and the size of the registers window | ||
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Example: | ||
sram@ff720000 { | ||
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; | ||
reg = <0xff720000 0x1000>; | ||
}; |
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SAMSUNG Exynos SoCs Chipid driver. | ||
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Required properties: | ||
- compatible : Should at least contain "samsung,exynos4210-chipid". | ||
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- reg: offset and length of the register set | ||
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Example: | ||
chipid@10000000 { | ||
compatible = "samsung,exynos4210-chipid"; | ||
reg = <0x10000000 0x100>; | ||
}; |
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Spreadtrum SoC Platforms Device Tree Bindings | ||
---------------------------------------------------- | ||
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Sharkl64 is a Spreadtrum's SoC Platform which is based | ||
on ARM 64-bit processor. | ||
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SC9836 openphone board with SC9836 SoC based on the | ||
Sharkl64 Platform shall have the following properties. | ||
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Required root node properties: | ||
- compatible = "sprd,sc9836-openphone", "sprd,sc9836"; |
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