Due date: Sunday 2/21/2016 @ 11:59pm

- Please remember to answer the questions in REPORT.txt

Objective:
~~~~~~~~~~

- Learn about RISC architectures

Assignment:
~~~~~~~~~~~

(1) Answer the questions in REPORT.txt

(2) Target the code generator from p4 to the PowerPC/64 architecture

This assignment will require some independent research in order to find
information about the PowerPC architecture and its instruction set:

Here are some highlights:

- RISC architecture (what does that mean?)

- 32 GPRS r0,r1, ..., r31

- 3-operand instructions: <op> dest,src0,src1

- Register-Register architecture: all operations have register operands

- With explicit load/store: you need to issue explicit instruction to
  get values into registers (load) or memory (store)

- Very few addressing modes:

    * immediate       -- li 4,100      # reg[4] = 100
    * register        -- add 6,7,8     # reg[6] = reg[7] + reg[8]
    * offset(base)    -- ld 2,-16(4)   # reg[2] = mem64[-16 + reg[4]]
    * index+base      -- ldx 3,4,5     # reg[3] = reg[4] + reg[5]

- The opcode determines the addressing mode:

    * li 5,100          # x86 mov $100,r5
                        # there is no need to say that 5 is a register
                        # and 100 is an immediate because that's what li does

    * add 3,4,5         # reg[3] = reg[4] + reg[5]

    * ld 8,100(12)      # reg[8] = mem64[100 + reg[12]]

- 16 bit immediates. How can you get any useful work done with that?

- No direct memory addressing. How are you going to access global variables?

- No hardware stack. R1 is used as the stack pointer by convention. Look for
  information on the load-with-update and store-with-update instructions

- The link register is used to save the return address

- Here are the instructions I used in my implementation (to help you get
  started)

    addi, b, bl, blr, beq, bgt, blt, bne, cmpd, cmpdi,
    ld, li, mflr, mtlr, or, std, stdu

- Look in ppc.asm for two useful pieces of code (not exactly functions)

- We don't have convenient access to PowerPC hardware so we have to run
  on our x86 boxes. This possible because we can:

     - Use cross-tools (specially built assembler and linker that run
       on x86 but produce binaries for PowerPC) to compile and link. 

       I stored those in /u/gheith/public/ppc64-linux/bin. The Makefile
       grabs them from there

    - Use an emulator to run the binaries (qemu-ppc64)

- You don't have to honor the PPC64 linkage convention but it's not a bad
  idea to read about it and understand the special role of r1 and r2

Files
~~~~~

p5.c      The compiler source (to be completed by you)
p5        The compiler executable (generated by "make p5")

For each test "tx"

tx.fun   the source program
tx.S      the equivalent x86-64 assembly program (generated by p5)
tx        the compiled program (generated by the Makefile)
tx.out    output produced by running tx
tx.ok     the expected output
tx.diff   the difference between tx.out tx.ok

Make targets:
~~~~~~~~~~~~~

make           # compile the compiler
make tx.S      # run the compiler on tx.fun and produce the x86-64 assembly
make tx        # run the compiler on tx.fun and produce the x86-64 executable
make tx.out    # run the compiled program and produce its output
make tx.diff   # produce the difference between tx.out and tx.ok
make tx.result # produce a summary of the result of running tx

make progs     # compile all the tests
make outs      # produce all the out files
make diffs     # produce all the diff files
make test      # produce summary output for all tests

Files to leave alone
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   Makefile
   t?.fun
   t?.ok

You can also add your own tests by creating a pair of
files (for example tz.fun and tx.ok)

To debug with gdb
~~~~~~~~~~~~~~~~~

    make
    gdb ./p5
    (gdb) run
    <<type your program>>
    <<terminate programing with ^D (pressing control and D together)

or

    gdb ./p5
    (gdb) run < t5.fun