In this project, we will design a 1-bit adder which is used to further design a 4-bit adder.
The objective of this project is to perform post-layout simulations. After verifying that the DRC and LVS have passed without any errors, we shall extract the parasitics to perform post-layout simulations. This will provide a clear understanding of the circuit speed, the effect of parasitics on the circuit, and any glitches introduced due to signal delay mismatches.
Unlike designing the layouts only with VDD and GND, which will not assure that the circuit will perform as desired. We will apply the required voltage and load to the pins in the layout to measure the performance of the circuit.
Steps followed to accomplish this:
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Creating a symbol of the standard cell.
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Creating a test bench using the symbol we created.
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Creating the layout of the standard cell.
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Observing the waveforms for transient simulation.
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Plotting waveforms for the extracted parasitics.
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Measuring the rising and falling delays from the waveform.
Important Notes to remember:
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To accomplish the optimal trade-off between area and frequency and to ensure that the worst-case and best-case delays of the circuit do not significantly differ from one another, we would prefer to match the rising and falling delays of the standard cells.
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Make sure the heights of all the common cell arrangements are equal. Because we will eventually use each of these gates to construct an adder circuit, we must arrange them close together. The Nwell areas of all the cells can be combined as well as the power lines VDD and GND when they are of the same height.
Next, we will use the standard cells to build a single-bit adder
Symbol of an Inverter:
Layout of an Inverter:
Circuit Under Test(CUT):
Delay Plots:
Falling delay for inverter cell is 2.57E-10 and the occurrence time is 3.05E-09
NAND:
Symbol of a NAND Gate:
Layout of a NAND:
Circuit Under Test (CUT):
Input-Output voltage Plots:
Extracted Parasitic Plots:
Delay Curve:
XOR Gate:
Symbol:
Layout:
Circuit Under Test(CUT):
Input-Output Voltage Curve:
Extracted Parasitic Curve:
Delay Plots:
Single-bit adder:
Layout:
Circuit Under Test(CUT):
Delay:
