This repository has been archived by the owner on Jun 7, 2023. It is now read-only.
Add: Verilog support. #108
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@bnmnetp, I'm using this in production on my server -- do you have any concerns about merging it? Do you want me to rebase this, or merge this, to bring it up to date with the main branch? |
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Oops, I don't know how I missed that. I rebased it and marked it as ready. |
bnmnetp
approved these changes
Nov 8, 2022
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