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University of Florida
- Gainesville
- @ruochen20
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EEE5716_Intro_to_hardware_securityRing-Oscillator-PUF-design-and-optimization-for-FPGA
EEE5716_Intro_to_hardware_securityRing-Oscillator-PUF-design-and-optimization-for-FPGA PublicIn this paper, a series of Ring Oscillators has been wired in different ways to form Ring Oscillator PUFs to find out the RO PUF which has a better quality. Thus, three different routing methods ar…
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EEE6323_AVLSI_32_Bit_Mips
EEE6323_AVLSI_32_Bit_Mips PublicThis project implements a 32-bit MIPS processor with forwarding and hazard detection module
Verilog
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EEL5721_Reconfigurable_Computing_1D_Time_Domain_Convolution
EEL5721_Reconfigurable_Computing_1D_Time_Domain_Convolution PublicIn this report, we implement an accelerated convolution calculator based on Xilinx Zynq. We divide whole process into 4 key steps(DRAM read/write Interface, Convolution Pipeline, Smart Buffer and K…
VHDL
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hackdac_2018_beta
hackdac_2018_beta PublicForked from hackdac/hackdac_2018_beta
The SoC used for the beta phase of Hack@DAC 2018.
SystemVerilog
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