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general3.c
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general3.c
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/* GENERAL3.C (C) Copyright Roger Bowler, 1994-2012 */
/* (C) and others 2013-2021 */
/* Hercules CPU Emulator - Additional General Instructions */
/* */
/* Released under "The Q Public License Version 1" */
/* (http://www.hercules-390.org/herclic.html) as modifications to */
/* Hercules. */
/*-------------------------------------------------------------------*/
/* This module implements additional general instructions introduced */
/* as later extensions to z/Architecture and described in the manual */
/* SA22-7832-06 z/Architecture Principles of Operation */
/*-------------------------------------------------------------------*/
#include "hstdinc.h"
#define _GENERAL3_C_
#define _HENGINE_DLL_
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
/* When an operation code has unused operand(s) (IPK, e.g.), it will */
/* attract a diagnostic for a set, but unused variable. Fixing the */
/* macros to support e.g., RS_NOOPS is not productive, so: */
DISABLE_GCC_UNUSED_SET_WARNING
#if defined( FEATURE_034_GEN_INST_EXTN_FACILITY )
#if defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )
/*-------------------------------------------------------------------*/
/* Perform Interlocked Storage Immediate Operation */
/* Subroutine called by ASI and ALSI instructions */
/*-------------------------------------------------------------------*/
/* EB6A ASI - Add Immediate Storage [SIY] */
/* EB6E ALSI - Add Logical with Signed Immediate [SIY] */
/*-------------------------------------------------------------------*/
DEF_INST(perform_interlocked_storage_immediate)
{
BYTE opcode; /* 2nd byte of opcode */
BYTE i2; /* Immediate byte */
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
BYTE *m1; /* Mainstor address */
U32 n; /* 32-bit operand value */
U32 result; /* Result value */
U32 old, new; /* Values for cmpxchg4 */
int cc; /* Condition code */
int rc; /* Return code */
SIY(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Extract second byte of instruction opcode */
opcode = inst[5];
/* Get mainstor address of storage operand */
m1 = MADDRL (effective_addr1, 4, b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
do {
/* Load 32-bit operand from operand address */
n = ARCH_DEP(vfetch4) (effective_addr1, b1, regs);
switch (opcode) {
case 0x6A: /* Add Storage Immediate */
/* Add signed operands and set condition code */
cc = add_signed (&result, n, (S32)(S8)i2);
break;
case 0x6E: /* Add Logical Storage with Signed Immediate */
/* Add operands and set condition code */
cc = (S8)i2 < 0 ?
sub_logical (&result, n, (S32)(-(S8)i2)) :
add_logical (&result, n, (S32)(S8)i2);
break;
default: /* To prevent compiler warnings */
result = 0;
cc = 0;
} /* end switch(opcode) */
/* Regular store if operand is not on a fullword boundary */
if ((effective_addr1 & 0x03) != 0) {
ARCH_DEP(vstore4) (result, effective_addr1, b1, regs);
break;
}
/* Interlocked exchange if operand is on a fullword boundary */
old = CSWAP32(n);
new = CSWAP32(result);
/* MAINLOCK may be required if cmpxchg assists unavailable */
OBTAIN_MAINLOCK( regs );
{
rc = cmpxchg4( &old, new, m1 );
}
RELEASE_MAINLOCK( regs );
} while (rc != 0);
/* Set condition code in PSW */
regs->psw.cc = cc;
} /* end DEF_INST(perform_interlocked_storage_immediate) */
/*-------------------------------------------------------------------*/
/* Perform Interlocked Long Storage Immediate Operation */
/* Subroutine called by AGSI and ALGSI instructions */
/*-------------------------------------------------------------------*/
/* EB7A AGSI - Add Immediate Long Storage [SIY] */
/* EB7E ALGSI - Add Logical with Signed Immediate Long [SIY] */
/*-------------------------------------------------------------------*/
DEF_INST(perform_interlocked_long_storage_immediate)
{
BYTE opcode; /* 2nd byte of opcode */
BYTE i2; /* Immediate byte */
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
BYTE *m1; /* Mainstor address */
U64 n; /* 64-bit operand value */
U64 result; /* Result value */
U64 old, new; /* Values for cmpxchg4 */
int cc; /* Condition code */
int rc; /* Return code */
SIY(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Extract second byte of instruction opcode */
opcode = inst[5];
/* Get mainstor address of storage operand */
m1 = MADDRL (effective_addr1, 8, b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
do {
/* Load 64-bit operand from operand address */
n = ARCH_DEP(vfetch8) (effective_addr1, b1, regs);
switch (opcode) {
case 0x7A: /* Add Long Storage Immediate */
/* Add signed operands and set condition code */
cc = add_signed_long (&result, n, (S64)(S8)i2);
break;
case 0x7E: /* Add Logical Long Storage with Signed Immediate */
/* Add operands and set condition code */
cc = (S8)i2 < 0 ?
sub_logical_long (&result, n, (S64)(-(S8)i2)) :
add_logical_long (&result, n, (S64)(S8)i2);
break;
default: /* To prevent compiler warnings */
result = 0;
cc = 0;
} /* end switch(opcode) */
/* Regular store if operand is not on a doubleword boundary */
if ((effective_addr1 & 0x07) != 0) {
ARCH_DEP(vstore8) (result, effective_addr1, b1, regs);
break;
}
/* Interlocked exchange if operand is on doubleword boundary */
old = CSWAP64(n);
new = CSWAP64(result);
/* MAINLOCK may be required if cmpxchg assists unavailable */
OBTAIN_MAINLOCK( regs );
{
rc = cmpxchg8( &old, new, m1 );
}
RELEASE_MAINLOCK( regs );
} while (rc != 0);
/* Set condition code in PSW */
regs->psw.cc = cc;
} /* end DEF_INST(perform_interlocked_long_storage_immediate) */
#endif /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )*/
/*-------------------------------------------------------------------*/
/* EB6A ASI - Add Immediate Storage [SIY] */
/*-------------------------------------------------------------------*/
DEF_INST(add_immediate_storage)
{
#if !defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )
BYTE i2; /* Immediate byte */
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
U32 n; /* 32-bit operand value */
int cc; /* Condition Code */
SIY(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 32-bit operand from operand address */
n = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
/* Add signed operands and set condition code */
cc = add_signed (&n, n, (S32)(S8)i2);
/* Store 32-bit operand at operand address */
ARCH_DEP(vstore4) ( n, effective_addr1, b1, regs );
/* Update Condition Code */
regs->psw.cc = cc;
#else /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 ) */
ARCH_DEP(perform_interlocked_storage_immediate) (inst, regs);
#endif /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )*/
/* Program check if fixed-point overflow */
if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
} /* end DEF_INST(add_immediate_storage) */
/*-------------------------------------------------------------------*/
/* EB7A AGSI - Add Immediate Long Storage [SIY] */
/*-------------------------------------------------------------------*/
DEF_INST(add_immediate_long_storage)
{
#if !defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )
BYTE i2; /* Immediate byte */
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
U64 n; /* 64-bit operand value */
int cc; /* Condition Code */
SIY(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 64-bit operand from operand address */
n = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
/* Add signed operands and set condition code */
cc = add_signed_long (&n, n, (S64)(S8)i2);
/* Store 64-bit value at operand address */
ARCH_DEP(vstore8) ( n, effective_addr1, b1, regs );
/* Update Condition Code */
regs->psw.cc = cc;
#else /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 ) */
ARCH_DEP(perform_interlocked_long_storage_immediate) (inst, regs);
#endif /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )*/
/* Program check if fixed-point overflow */
if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
} /* end DEF_INST(add_immediate_long_storage) */
/*-------------------------------------------------------------------*/
/* EB6E ALSI - Add Logical with Signed Immediate [SIY] */
/*-------------------------------------------------------------------*/
DEF_INST(add_logical_with_signed_immediate)
{
#if !defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )
BYTE i2; /* Immediate byte */
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
U32 n; /* 32-bit operand value */
int cc; /* Condition Code */
SIY(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 32-bit operand from operand address */
n = ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
/* Add operands and set condition code */
cc = (S8)i2 < 0 ?
sub_logical (&n, n, (S32)(-(S8)i2)) :
add_logical (&n, n, (S32)(S8)i2);
/* Store 32-bit operand at operand address */
ARCH_DEP(vstore4) ( n, effective_addr1, b1, regs );
/* Update Condition Code */
regs->psw.cc = cc;
#else /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 ) */
ARCH_DEP(perform_interlocked_storage_immediate) (inst, regs);
#endif /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )*/
} /* end DEF_INST(add_logical_with_signed_immediate) */
/*-------------------------------------------------------------------*/
/* EB7E ALGSI - Add Logical with Signed Immediate Long [SIY] */
/*-------------------------------------------------------------------*/
DEF_INST(add_logical_with_signed_immediate_long)
{
#if !defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )
BYTE i2; /* Immediate byte */
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
U64 n; /* 64-bit operand value */
int cc; /* Condition Code */
SIY(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 64-bit operand from operand address */
n = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
/* Add operands and set condition code */
cc = (S8)i2 < 0 ?
sub_logical_long (&n, n, (S64)(-(S8)i2)) :
add_logical_long (&n, n, (S64)(S8)i2);
/* Store 64-bit value at operand address */
ARCH_DEP(vstore8) ( n, effective_addr1, b1, regs );
/* Update Condition Code */
regs->psw.cc = cc;
#else /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 ) */
ARCH_DEP(perform_interlocked_long_storage_immediate) (inst, regs);
#endif /* defined( FEATURE_045_INTERLOCKED_ACCESS_FACILITY_1 )*/
} /* end DEF_INST(add_logical_with_signed_immediate_long) */
/*-------------------------------------------------------------------*/
/* ECF6 CRB - Compare and Branch Register [RRS] */
/*-------------------------------------------------------------------*/
DEF_INST( compare_and_branch_register )
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int b4; /* Base of effective addr */
VADR effective_addr4; /* Effective address */
int cc; /* Comparison result */
RRS_B( inst, regs, r1, r2, m3, b4, effective_addr4 );
TXFC_INSTR_CHECK_IP( regs );
/* Compare signed operands and set comparison result */
cc = (S32)regs->GR_L(r1) < (S32)regs->GR_L(r2) ? 1 :
(S32)regs->GR_L(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
/* Branch to operand address if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_BRANCH( regs, effective_addr4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_and_branch_register) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* ECE4 CGRB - Compare and Branch Long Register [RRS] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_and_branch_long_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int b4; /* Base of effective addr */
VADR effective_addr4; /* Effective address */
int cc; /* Comparison result */
RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
TXFC_INSTR_CHECK_IP( regs );
/* Compare signed operands and set comparison result */
cc = (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
(S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
/* Branch to operand address if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_BRANCH( regs, effective_addr4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_and_branch_long_register) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* EC76 CRJ - Compare and Branch Relative Register [RIE-b] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_and_branch_relative_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
S16 i4; /* 16-bit immediate offset */
int cc; /* Comparison result */
RIE_RRIM_B(inst, regs, r1, r2, i4, m3);
TXFC_BRANCH_CHECK_IP( regs, m3, i4 );
/* Compare signed operands and set comparison result */
cc = (S32)regs->GR_L(r1) < (S32)regs->GR_L(r2) ? 1 :
(S32)regs->GR_L(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
/* Branch to immediate offset if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_RELATIVE_BRANCH( regs, 2LL*i4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_and_branch_relative_register) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* EC64 CGRJ - Compare and Branch Relative Long Register [RIE-b] */
/*-------------------------------------------------------------------*/
DEF_INST( compare_and_branch_relative_long_register )
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
S16 ri4; /* 16-bit relative offset */
int cc; /* Comparison result */
RIE_RRIM_B( inst, regs, r1, r2, ri4, m3 );
TXFC_BRANCH_CHECK_IP( regs, m3, ri4 );
/* Compare signed operands and set comparison result */
cc = (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
(S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
/* Branch to immediate offset if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_RELATIVE_BRANCH( regs, 2LL*ri4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST( compare_and_branch_relative_long_register ) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* B972 CRT - Compare and Trap Register [RRF-c] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_and_trap_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int cc; /* Comparison result */
RRF_M(inst, regs, r1, r2, m3);
/* Compare signed operands and set comparison result */
cc = (S32)regs->GR_L(r1) < (S32)regs->GR_L(r2) ? 1 :
(S32)regs->GR_L(r1) > (S32)regs->GR_L(r2) ? 2 : 0;
/* Raise data exception if m3 mask bit is set */
if ((0x8 >> cc) & m3)
{
regs->dxc = DXC_COMPARE_AND_TRAP;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(compare_and_trap_register) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* B960 CGRT - Compare and Trap Long Register [RRF-c] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_and_trap_long_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int cc; /* Comparison result */
RRF_M(inst, regs, r1, r2, m3);
/* Compare signed operands and set comparison result */
cc = (S64)regs->GR_G(r1) < (S64)regs->GR_G(r2) ? 1 :
(S64)regs->GR_G(r1) > (S64)regs->GR_G(r2) ? 2 : 0;
/* Raise data exception if m3 mask bit is set */
if ((0x8 >> cc) & m3)
{
regs->dxc = DXC_COMPARE_AND_TRAP;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(compare_and_trap_long_register) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* E554 CHHSI - Compare Halfword Immediate Halfword Storage [SIL] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_immediate_halfword_storage)
{
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
S16 i2; /* 16-bit immediate value */
S16 n; /* 16-bit storage value */
SIL(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 16-bit value from first operand address */
n = (S16)ARCH_DEP(vfetch2) ( effective_addr1, b1, regs );
/* Compare signed operands and set condition code */
regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
} /* end DEF_INST(compare_halfword_immediate_halfword_storage) */
/*-------------------------------------------------------------------*/
/* E558 CGHSI - Compare Halfword Immediate Long Storage [SIL] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_immediate_long_storage)
{
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
S16 i2; /* 16-bit immediate value */
S64 n; /* 64-bit storage value */
SIL(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 64-bit value from first operand address */
n = (S64)ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
/* Compare signed operands and set condition code */
regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
} /* end DEF_INST(compare_halfword_immediate_long_storage) */
/*-------------------------------------------------------------------*/
/* E55C CHSI - Compare Halfword Immediate Storage [SIL] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_immediate_storage)
{
int b1; /* Base of effective addr */
VADR effective_addr1; /* Effective address */
S16 i2; /* 16-bit immediate value */
S32 n; /* 32-bit storage value */
SIL(inst, regs, i2, b1, effective_addr1);
PER_ZEROADDR_XCHECK( regs, b1 );
/* Load 32-bit value from first operand address */
n = (S32)ARCH_DEP(vfetch4) ( effective_addr1, b1, regs );
/* Compare signed operands and set condition code */
regs->psw.cc = n < i2 ? 1 : n > i2 ? 2 : 0;
} /* end DEF_INST(compare_halfword_immediate_storage) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* E334 CGH - Compare Halfword Long [RXY-a] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_long)
{
int r1; /* Values of R fields */
int x2; /* Index register */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S64 n; /* 64-bit operand value */
RXY(inst, regs, r1, x2, b2, effective_addr2);
PER_ZEROADDR_XCHECK2( regs, x2, b2 );
/* Load rightmost 2 bytes of comparand from operand address */
n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
/* Compare signed operands and set condition code */
regs->psw.cc =
(S64)regs->GR_G(r1) < n ? 1 :
(S64)regs->GR_G(r1) > n ? 2 : 0;
} /* end DEF_INST(compare_halfword_long) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* C6x5 CHRL - Compare Halfword Relative Long [RIL-b] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_relative_long)
{
int r1; /* Register number */
VADR effective_addr2; /* Relative operand address */
U16 n; /* Relative operand value */
RIL_A(inst, regs, r1, effective_addr2);
/* Load relative operand from instruction address space */
n = ARCH_DEP(vfetch2) ( effective_addr2, USE_INST_SPACE, regs );
/* Compare signed operands and set condition code */
regs->psw.cc =
(S32)regs->GR_L(r1) < (S16)n ? 1 :
(S32)regs->GR_L(r1) > (S16)n ? 2 : 0;
} /* end DEF_INST(compare_halfword_relative_long) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* C6x4 CGHRL - Compare Halfword Relative Long Long [RIL-b] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_halfword_relative_long_long)
{
int r1; /* Register number */
VADR effective_addr2; /* Relative operand address */
U16 n; /* Relative operand value */
RIL_A(inst, regs, r1, effective_addr2);
/* Load relative operand from instruction address space */
n = ARCH_DEP(vfetch2) ( effective_addr2, USE_INST_SPACE, regs );
/* Compare signed operands and set condition code */
regs->psw.cc =
(S64)regs->GR_G(r1) < (S16)n ? 1 :
(S64)regs->GR_G(r1) > (S16)n ? 2 : 0;
} /* end DEF_INST(compare_halfword_relative_long_long) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* ECFE CIB - Compare Immediate and Branch [RIS] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_branch)
{
int r1; /* Register number */
int m3; /* Mask bits */
int b4; /* Base of effective addr */
VADR effective_addr4; /* Effective address */
int cc; /* Comparison result */
BYTE i2; /* Immediate value */
RIS_B(inst, regs, r1, i2, m3, b4, effective_addr4);
TXFC_INSTR_CHECK_IP( regs );
/* Compare signed operands and set comparison result */
cc = (S32)regs->GR_L(r1) < (S32)(S8)i2 ? 1 :
(S32)regs->GR_L(r1) > (S32)(S8)i2 ? 2 : 0;
/* Branch to operand address if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_BRANCH( regs, effective_addr4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_immediate_and_branch) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* ECFC CGIB - Compare Immediate and Branch Long [RIS] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_branch_long)
{
int r1; /* Register number */
int m3; /* Mask bits */
int b4; /* Base of effective addr */
VADR effective_addr4; /* Effective address */
int cc; /* Comparison result */
BYTE i2; /* Immediate value */
RIS_B(inst, regs, r1, i2, m3, b4, effective_addr4);
TXFC_INSTR_CHECK_IP( regs );
/* Compare signed operands and set comparison result */
cc = (S64)regs->GR_G(r1) < (S64)(S8)i2 ? 1 :
(S64)regs->GR_G(r1) > (S64)(S8)i2 ? 2 : 0;
/* Branch to operand address if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_BRANCH( regs, effective_addr4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_immediate_and_branch_long) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* EC7E CIJ - Compare Immediate and Branch Relative [RIE-c] */
/*-------------------------------------------------------------------*/
DEF_INST( compare_immediate_and_branch_relative )
{
int r1; /* Register numbers */
int m3; /* Mask bits */
BYTE i2; /* Immediate operand value */
S16 ri4; /* 16-bit relative offset */
int cc; /* Comparison result */
RIE_RMII_B( inst, regs, r1, i2, m3, ri4 );
TXFC_BRANCH_CHECK_IP( regs, m3, ri4 );
/* Compare signed operands and set comparison result */
cc = (S32)regs->GR_L(r1) < (S32)(S8)i2 ? 1 :
(S32)regs->GR_L(r1) > (S32)(S8)i2 ? 2 : 0;
/* Branch to immediate offset if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_RELATIVE_BRANCH( regs, 2LL*ri4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST( compare_immediate_and_branch_relative ) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* EC7C CGIJ - Compare Immediate and Branch Relative Long [RIE-c] */
/*-------------------------------------------------------------------*/
DEF_INST( compare_immediate_and_branch_relative_long )
{
int r1; /* Register numbers */
int m3; /* Mask bits */
BYTE i2; /* Immediate operand value */
S16 ri4; /* 16-bit relative offset */
int cc; /* Comparison result */
RIE_RMII_B( inst, regs, r1, i2, m3, ri4 );
TXFC_BRANCH_CHECK_IP( regs, m3, ri4 );
/* Compare signed operands and set comparison result */
cc = (S64)regs->GR_G(r1) < (S64)(S8)i2 ? 1 :
(S64)regs->GR_G(r1) > (S64)(S8)i2 ? 2 : 0;
/* Branch to immediate offset if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_RELATIVE_BRANCH( regs, 2LL*ri4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST( compare_immediate_and_branch_relative_long ) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* EC72 CIT - Compare Immediate and Trap [RIE-a] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_trap)
{
int r1; /* Register number */
int m3; /* Mask bits */
int cc; /* Comparison result */
U16 i2; /* 16-bit immediate value */
RIE_RIM(inst, regs, r1, i2, m3);
/* Compare signed operands and set comparison result */
cc = (S32)regs->GR_L(r1) < (S32)(S16)i2 ? 1 :
(S32)regs->GR_L(r1) > (S32)(S16)i2 ? 2 : 0;
/* Raise data exception if m3 mask bit is set */
if ((0x8 >> cc) & m3)
{
regs->dxc = DXC_COMPARE_AND_TRAP;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(compare_immediate_and_trap) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* EC70 CGIT - Compare Immediate and Trap Long [RIE-a] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_immediate_and_trap_long)
{
int r1; /* Register number */
int m3; /* Mask bits */
int cc; /* Comparison result */
U16 i2; /* 16-bit immediate value */
RIE_RIM(inst, regs, r1, i2, m3);
/* Compare signed operands and set comparison result */
cc = (S64)regs->GR_G(r1) < (S64)(S16)i2 ? 1 :
(S64)regs->GR_G(r1) > (S64)(S16)i2 ? 2 : 0;
/* Raise data exception if m3 mask bit is set */
if ((0x8 >> cc) & m3)
{
regs->dxc = DXC_COMPARE_AND_TRAP;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(compare_immediate_and_trap_long) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* ECF7 CLRB - Compare Logical and Branch Register [RRS] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int b4; /* Base of effective addr */
VADR effective_addr4; /* Effective address */
int cc; /* Comparison result */
RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
TXFC_INSTR_CHECK_IP( regs );
/* Compare unsigned operands and set comparison result */
cc = regs->GR_L(r1) < regs->GR_L(r2) ? 1 :
regs->GR_L(r1) > regs->GR_L(r2) ? 2 : 0;
/* Branch to operand address if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_BRANCH( regs, effective_addr4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_logical_and_branch_register) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* ECE5 CLGRB - Compare Logical and Branch Long Register [RRS] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_long_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int b4; /* Base of effective addr */
VADR effective_addr4; /* Effective address */
int cc; /* Comparison result */
RRS_B(inst, regs, r1, r2, m3, b4, effective_addr4);
TXFC_INSTR_CHECK_IP( regs );
/* Compare unsigned operands and set comparison result */
cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
/* Branch to operand address if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_BRANCH( regs, effective_addr4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_logical_and_branch_long_register) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* EC77 CLRJ - Compare Logical and Branch Relative Register [RIE-b] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_relative_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
S16 ri4; /* 16-bit relative offset */
int cc; /* Comparison result */
RIE_RRIM_B( inst, regs, r1, r2, ri4, m3 );
TXFC_BRANCH_CHECK_IP( regs, m3, ri4 );
/* Compare unsigned operands and set comparison result */
cc = regs->GR_L(r1) < regs->GR_L(r2) ? 1 :
regs->GR_L(r1) > regs->GR_L(r2) ? 2 : 0;
/* Branch to immediate offset if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_RELATIVE_BRANCH( regs, 2LL*ri4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_logical_and_branch_relative_register) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* EC65 CLGRJ - Compare Logical and Branch Relative Long Reg [RIE-b] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_branch_relative_long_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
S16 ri4; /* 16-bit relative offset */
int cc; /* Comparison result */
RIE_RRIM_B( inst, regs, r1, r2, ri4, m3 );
TXFC_BRANCH_CHECK_IP( regs, m3, ri4 );
/* Compare unsigned operands and set comparison result */
cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
/* Branch to immediate offset if m3 mask bit is set */
if ((0x8 >> cc) & m3)
SUCCESSFUL_RELATIVE_BRANCH( regs, 2LL*ri4 );
else
{
/* Bump ip to next sequential instruction */
regs->ip += 6;
}
} /* end DEF_INST(compare_logical_and_branch_relative_long_register) */
#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/*-------------------------------------------------------------------*/
/* B973 CLRT - Compare Logical and Trap Register [RRF-c] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_trap_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int cc; /* Comparison result */
RRF_M(inst, regs, r1, r2, m3);
/* Compare unsigned operands and set comparison result */
cc = regs->GR_L(r1) < regs->GR_L(r2) ? 1 :
regs->GR_L(r1) > regs->GR_L(r2) ? 2 : 0;
/* Raise data exception if m3 mask bit is set */
if ((0x8 >> cc) & m3)
{
regs->dxc = DXC_COMPARE_AND_TRAP;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(compare_logical_and_trap_register) */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/*-------------------------------------------------------------------*/
/* B961 CLGRT - Compare Logical and Trap Long Register [RRF-c] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_logical_and_trap_long_register)
{
int r1, r2; /* Register numbers */
int m3; /* Mask bits */
int cc; /* Comparison result */
RRF_M(inst, regs, r1, r2, m3);
/* Compare unsigned operands and set comparison result */
cc = regs->GR_G(r1) < regs->GR_G(r2) ? 1 :
regs->GR_G(r1) > regs->GR_G(r2) ? 2 : 0;
/* Raise data exception if m3 mask bit is set */
if ((0x8 >> cc) & m3)
{
regs->dxc = DXC_COMPARE_AND_TRAP;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}