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Updated README #1

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Updated README #1

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NachtSpyder04
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Changes made in README:-

  • Removed whiteboard diagram of CPU
  • Added installation paths for used softwares
  • Updated and added new command for simulation and for flashing on FPGA

README.md Outdated
@@ -1,4 +1,4 @@
# RISC-V-Eklavya'23
# RISC-V-CPU
---

#### The RISC-V CPU will be implemented with IMAF instruction extensions, and also verified using custom verification methods.
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Let’s not talk about future objectives, and try to describe the CPU in its current. State. The first thing in a README should be describing what we have in the repository.

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Ok, will do the changes

README.md Outdated
@@ -10,14 +10,45 @@ RISC-V is an instruction set architecture like ARM based on RISC (Reduced Instr

Due to being open-source in nature, RISC-V provides a vital step in designing, building and testing new hardware without paying any license fees or royalties
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This seems unnecessary.

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Ok, will remove that section.

README.md Outdated
---
### How to compile the CPU and view simulation

First we need to write a C code for the operation we need to perform on our CPU(For example:- We have written a script that generates fibonacci series),
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Why are you writing this para as “We”. Reword this paragraph simply as instructions.

“An example C program can be loaded on the CPU’s program memory for operations.”
“We provide an example code under sim/fibonacci.c for testing purposes."

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Ok, will do the changes

README.md Outdated
-[Verilator](https://verilator.org/guide/latest/install.html)
-[Gtkwave](https://gtkwave.sourceforge.net/)

All the necessary commands have been added to the Makefile
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Specify path of the makefile

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Ok, will do the changes

@@ -48,20 +79,21 @@ Following is the block diagram and workflow in simple terms of our CPU:-
![image.png](https://hackmd.io/_uploads/rJScfOEXT.png)


![image.png](https://hackmd.io/_uploads/rk-YYoMXp.png)

---

### Tech Stack

- Verilog
- Quartus Prime IDE
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Remove this as we no longer use it.

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Ok, will do the changes

README.md Outdated
- Lattice Framework
---
### Future Work
- [ ] Fix issues with Seven Segment Display
- [ ] Verify CPU output with every cases, possible, edge and false cases.
- [x] Verify CPU output with every cases, possible, edge and false cases.
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Verification is not done. Ideally, there should be a script that will formally verify the CPU and display results.

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Ok, will do the changes.

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Please add instructions or a list of software which are needed to run the CPU. Provide links with instructions to install/build.

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@NachtSpyder04 NachtSpyder04 Jan 14, 2024

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I have added softwares in the Tech stack, should I bring it on top of the document?

Also links for installations are also given above in the form of hyperlinks

@SuperChamp234 SuperChamp234 added the documentation Improvements or additions to documentation label Jan 14, 2024
@NachtSpyder04
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Pushed the suggested changes
Please review it to see if it is appropriate or not

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