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stm32f4xx_hal_rcc_ex.h
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stm32f4xx_hal_rcc_ex.h
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/**
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_RCC_EX_H
#define __STM32F4xx_HAL_RCC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup RCCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
* @{
*/
/**
* @brief RCC PLL configuration structure definition
*/
typedef struct
{
uint32_t PLLState; /*!< The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432
except for STM32F411xE devices where the Min_Data = 192 */
uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
defined(STM32F413xx) || defined(STM32F423xx)
uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
}RCC_PLLInitTypeDef;
#if defined(STM32F446xx)
/**
* @brief PLLI2S Clock structure definition
*/
typedef struct
{
uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLI2S is selected as Clock Source I2S */
}RCC_PLLI2SInitTypeDef;
/**
* @brief PLLSAI Clock structure definition
*/
typedef struct
{
uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLSAI is selected as Clock Source SAI */
}RCC_PLLSAIInitTypeDef;
/**
* @brief RCC extended clocks structure definition
*/
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLLSAI is selected as Clock Source SAI */
uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F446xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
/**
* @brief RCC extended clocks structure definition
*/
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief PLLI2S Clock structure definition
*/
typedef struct
{
uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLI2S is selected as Clock Source I2S */
}RCC_PLLI2SInitTypeDef;
/**
* @brief RCC extended clocks structure definition
*/
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source I2S */
#if defined(STM32F413xx) || defined(STM32F423xx)
uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLL is selected as Clock Source SAI */
uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
#endif /* STM32F413xx || STM32F423xx */
uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
#if defined(STM32F413xx) || defined(STM32F423xx)
uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
#endif /* STM32F413xx || STM32F423xx */
uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief PLLI2S Clock structure definition
*/
typedef struct
{
uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
}RCC_PLLI2SInitTypeDef;
/**
* @brief PLLSAI Clock structure definition
*/
typedef struct
{
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432.
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
#if defined(STM32F469xx) || defined(STM32F479xx)
uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
This parameter is only available in STM32F469xx/STM32F479xx devices.
This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
#endif /* STM32F469xx || STM32F479xx */
uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
}RCC_PLLSAIInitTypeDef;
/**
* @brief RCC extended clocks structure definition
*/
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLLSAI is selected as Clock Source SAI */
uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
#if defined(STM32F469xx) || defined(STM32F479xx)
uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
#endif /* STM32F469xx || STM32F479xx */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/**
* @brief PLLI2S Clock structure definition
*/
typedef struct
{
#if defined(STM32F411xE)
uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
#endif /* STM32F411xE */
uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 50 and Max_Data = 432
Except for STM32F411xE devices where the Min_Data = 192.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
}RCC_PLLI2SInitTypeDef;
/**
* @brief RCC extended clocks structure definition
*/
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
* @{
*/
/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
* @{
*/
/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
defined(STM32F413xx) || defined(STM32F423xx)
#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
#define RCC_PERIPHCLK_TIM 0x00000004U
#define RCC_PERIPHCLK_RTC 0x00000008U
#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
#define RCC_PERIPHCLK_CLK48 0x00000020U
#define RCC_PERIPHCLK_SDIO 0x00000040U
#define RCC_PERIPHCLK_PLLI2S 0x00000080U
#define RCC_PERIPHCLK_DFSDM1 0x00000100U
#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
#if defined(STM32F413xx) || defined(STM32F423xx)
#define RCC_PERIPHCLK_DFSDM2 0x00000400U
#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
#define RCC_PERIPHCLK_LPTIM1 0x00001000U
#define RCC_PERIPHCLK_SAIA 0x00002000U
#define RCC_PERIPHCLK_SAIB 0x00004000U
#endif /* STM32F413xx || STM32F423xx */
/*----------------------------------------------------------------------------*/
/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
#define RCC_PERIPHCLK_I2S 0x00000001U
#define RCC_PERIPHCLK_TIM 0x00000002U
#define RCC_PERIPHCLK_RTC 0x00000004U
#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
#define RCC_PERIPHCLK_LPTIM1 0x00000010U
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
/*----------------------------------------------------------------------------*/
/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
#if defined(STM32F446xx)
#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
#define RCC_PERIPHCLK_SAI1 0x00000004U
#define RCC_PERIPHCLK_SAI2 0x00000008U
#define RCC_PERIPHCLK_TIM 0x00000010U
#define RCC_PERIPHCLK_RTC 0x00000020U
#define RCC_PERIPHCLK_CEC 0x00000040U
#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
#define RCC_PERIPHCLK_CLK48 0x00000100U
#define RCC_PERIPHCLK_SDIO 0x00000200U
#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
#define RCC_PERIPHCLK_PLLI2S 0x00000800U
#endif /* STM32F446xx */
/*-----------------------------------------------------------------------------*/
/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
#if defined(STM32F469xx) || defined(STM32F479xx)
#define RCC_PERIPHCLK_I2S 0x00000001U
#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
#define RCC_PERIPHCLK_LTDC 0x00000008U
#define RCC_PERIPHCLK_TIM 0x00000010U
#define RCC_PERIPHCLK_RTC 0x00000020U
#define RCC_PERIPHCLK_PLLI2S 0x00000040U
#define RCC_PERIPHCLK_CLK48 0x00000080U
#define RCC_PERIPHCLK_SDIO 0x00000100U
#endif /* STM32F469xx || STM32F479xx */
/*----------------------------------------------------------------------------*/
/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#define RCC_PERIPHCLK_I2S 0x00000001U
#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
#define RCC_PERIPHCLK_LTDC 0x00000008U
#define RCC_PERIPHCLK_TIM 0x00000010U
#define RCC_PERIPHCLK_RTC 0x00000020U
#define RCC_PERIPHCLK_PLLI2S 0x00000040U
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
/*----------------------------------------------------------------------------*/
/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define RCC_PERIPHCLK_I2S 0x00000001U
#define RCC_PERIPHCLK_RTC 0x00000002U
#define RCC_PERIPHCLK_PLLI2S 0x00000004U
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
#define RCC_PERIPHCLK_TIM 0x00000008U
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
/*----------------------------------------------------------------------------*/
/**
* @}
*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
defined(STM32F479xx)
/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
#define RCC_I2SCLKSOURCE_EXT 0x00000001U
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
#define RCC_PLLSAIDIVR_2 0x00000000U
#define RCC_PLLSAIDIVR_4 0x00010000U
#define RCC_PLLSAIDIVR_8 0x00020000U
#define RCC_PLLSAIDIVR_16 0x00030000U
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
* @{
*/
#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx)
#define RCC_PLLI2SP_DIV2 0x00000002U
#define RCC_PLLI2SP_DIV4 0x00000004U
#define RCC_PLLI2SP_DIV6 0x00000006U
#define RCC_PLLI2SP_DIV8 0x00000008U
#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
/**
* @}
*/
/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
* @{
*/
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define RCC_PLLSAIP_DIV2 0x00000002U
#define RCC_PLLSAIP_DIV4 0x00000004U
#define RCC_PLLSAIP_DIV6 0x00000006U
#define RCC_PLLSAIP_DIV8 0x00000008U
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
* @{
*/
#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
#define RCC_SAIACLKSOURCE_EXT 0x00200000U
/**
* @}
*/
/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
* @{
*/
#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
/**
* @}
*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
* @{
*/
#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
/**
* @}
*/
/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
* @{
*/
#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
/**
* @}
*/
/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
* @{
*/
#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
/**
* @}
*/
#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F446xx)
/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
* @{
*/
#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
/**
* @}
*/
/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
* @{
*/
#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
/**
* @}
*/
/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
* @{
*/
#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
/**
* @}
*/
/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
* @{
*/
#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
/**
* @}
*/
/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
* @{
*/
#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
* @{
*/
#define RCC_CECCLKSOURCE_HSI 0x00000000U
#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
/**
* @}
*/
/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
* @{
*/
#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
/**
* @}
*/
/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
* @{
*/
#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
/**
* @}
*/
/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
* @{
*/
#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
/**
* @}
*/
#endif /* STM32F446xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
* @{
*/
#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
/**
* @}
*/
/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
* @{
*/
#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
/**
* @}
*/
/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
* @{
*/
#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
* @{
*/
#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
/**
* @}
*/
/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
* @{
*/
#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
/**
* @}
*/
#endif /* STM32F413xx || STM32F423xx */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
* @{
*/
#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
/**
* @}
*/
/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
* @{
*/
#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
/**
* @}
*/
/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
* @{
*/
#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
/**
* @}
*/
/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
* @{
*/
#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
/**
* @}
*/
/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
* @{
*/
#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
/**
* @}
*/
/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
* @{
*/
#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
* @{
*/
#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
/**
* @}
*/
/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
* @{
*/
#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
/**
* @}
*/
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
* @{
*/
#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
/**
* @}
*/
/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
* @{
*/
#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
* @{
*/
#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
/**
* @}
*/
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
* @{
*/
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
/**
* @}
*/
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
defined(STM32F423xx)
/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
* @{
*/
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
/**
* @}
*/
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
STM32F412Rx || STM32F412Cx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
/**
* @}
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
STM32F412Rx || STM32F413xx | STM32F423xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
/**
* @}
*/
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
*/
/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
* @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \