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Release v1.3.1
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ALABSTM committed Nov 8, 2023
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2 changes: 1 addition & 1 deletion Include/Templates/partition_stm32u595xx.h
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******************************************************************************
* @file partition_stm32u595xx.h
* @author MCD Application Team
* @brief CMSIS STM32U599xx Device Initial Setup for Secure / Non-Secure Zones
* @brief CMSIS STM32U595xx Device Initial Setup for Secure / Non-Secure Zones
* for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template.
*
* This file contains:
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4 changes: 2 additions & 2 deletions Include/Templates/partition_stm32u5f7xx.h
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/**
******************************************************************************
* @file partition_stm32u5f9xx.h
* @file partition_stm32u5f7xx.h
* @author MCD Application Team
* @brief CMSIS STM32U5F9xx Device Initial Setup for Secure / Non-Secure Zones
* @brief CMSIS STM32U5F7xx Device Initial Setup for Secure / Non-Secure Zones
* for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template.
*
* This file contains:
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14 changes: 7 additions & 7 deletions Include/stm32u5xx.h
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/* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
/* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */
/* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */
/* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q Devices */
/* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */
/* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */
/* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 Devices STM32U5F7VIT6Q STM32U5F7VIT6 Devices */
/* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */
/* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */
/* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q Devices */
/* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */
/* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */
/* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */
/* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */
/* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */
/* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */
#endif

/* Tip: To avoid modifying this file each time you need to switch between these
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#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number 1.3.0
* @brief CMSIS Device version number 1.3.1
*/
#define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32U5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32U5_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
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28 changes: 21 additions & 7 deletions Release_Notes.html
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Expand Up @@ -30,19 +30,33 @@ <h1 id="release-notes-for-stm32u5xx-cmsis">Release Notes for <mark> STM32U5xx C
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" checked aria-hidden="true"><strong>V1.3.0 / 09-June-2023</strong></label>
<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" checked aria-hidden="true"><strong>V1.3.1 / 20-October-2023</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<p><strong>CMSIS Device</strong> Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)</p>
<ul>
<li>Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file</li>
</ul>
<h2 id="backward-compatibility">Backward Compatibility</h2>
<ul>
<li>N/A</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" checked aria-hidden="true"><strong>V1.3.0 / 09-June-2023</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<p><strong>CMSIS Device</strong> Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)</p>
<ul>
<li><strong>Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices</strong>:
<ul>
<li>Add “stm32u5f9xx.h”, “stm32u5g9xx.h”, “stm32u5f7xx.h” and “stm32u5g7xx.h” files</li>
<li>Add startup files “startup_stm32u5f9xx.s”, “startup_stm32u5g9xx.s”, “startup_stm32u5f7xx.s” and “startup_stm32u5g7xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains</li>
<li>Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices</li>
</ul></li>
</ul>
<h2 id="backward-compatibility">Backward Compatibility</h2>
<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<ul>
<li>N/A</li>
</ul>
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<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.2.0 / 08-June-2023</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<h2 id="main-changes-2">Main Changes</h2>
<p><strong>CMSIS Device</strong> Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)</p>
<ul>
<li><strong>Support of stm32u535xx and stm32u545xx devices</strong>:
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<li>Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP</li>
</ul></li>
</ul>
<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<ul>
<li>N/A</li>
</ul>
Expand All @@ -113,7 +127,7 @@ <h2 id="backward-compatibility-1">Backward Compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" checked aria-hidden="true"><strong>V1.1.0 / 16-February-2022</strong></label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li><strong>CMSIS Device</strong> Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
<ul>
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<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.0.1 / 01-October-2021</strong></label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define</li>
<li>Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define</li>
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<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 28-June-2021</strong></label>
<div>
<h2 id="main-changes-4">Main Changes</h2>
<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)</li>
</ul>
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