stm32mp135f-dk.dts

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */

/dts-v1/;

#include <dt-bindings/clock/stm32mp13-clksrc.h>
#include <dt-bindings/power/stm32mp1-power.h>
#include <dt-bindings/random/stm32mp-rng.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include <dt-bindings/soc/stm32mp-tzc400-macro.h>
#include <dt-bindings/soc/stm32mp13-etzpc.h>
#include <dt-bindings/soc/stm32mp13-tzc400.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-pinctrl.dtsi"

/ {
	model = "STMicroelectronics STM32MP135F-DK Discovery Board";
	compatible = "st,stm32mp135f-dk", "st,stm32mp135";

	aliases {
		serial0 = &uart4;
		serial1 = &usart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	magic_wol: magic_wol {
		compatible = "st,stm32mp1,pwr-irq-user";
		st,wakeup-pin-number = <2>;
		status = "okay";
	};

	memory@c0000000 {
		device_type = "memory";
		reg = <0xc0000000 0x20000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		optee_framebuffer: optee-framebuffer@dd000000 {
			/* Secure framebuffer memory */
			reg = <0xdd000000 0x1000000>;
			st,protreg = <TZC_REGION_S_RDWR 0>;
		};
	};

	vin: vin {
		compatible = "regulator-fixed";
		regulator-name = "vin";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	v3v3_ao: v3v3_ao {
		compatible = "regulator-fixed";
		regulator-name = "v3v3_ao";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	typec_wakeup: typec_wakeup {
		compatible = "st,stm32mp1,pwr-irq-user";
		/* Alert pin on PI2, wakeup_pin_5 */
		st,wakeup-pin-number = <5>;
		st,notif-it-id = <1>;
		status = "okay";
	};
};

&adc_2 {
	vdda-supply = <&vdd_adc>;
	vref-supply = <&vdd_adc>;
	status = "okay";

	adc2: adc@0 {
		status = "okay";

		channel@15 {
			reg = <15>;
			label = "vbat";
		};
	};
};

&bsec {
	board_id: board_id@f0 {
		reg = <0xf0 0x4>;
		st,non-secure-otp;
	};
};

&cpu0 {
	cpu-supply = <&vddcpu>;
};

&etzpc {
	st,decprot = <
		DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	>;
};

&gpiob {
	st,protreg = < (TZPROT(9)) >;
};

&gpiod {
	st,protreg = < (TZPROT(7)) >;
};

&gpioe {
	st,protreg = < (TZPROT(15)) >;
};

&gpioi {
	st,protreg = < (TZPROT(2)|TZPROT(3)) >;
};

&hash {
	status = "okay";
};

&hse_monitor {
	status = "okay";
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	clock-frequency = <400000>;
	status = "okay";

	pmic: stpmic@33 {
		compatible = "st,stpmic1";
		reg = <0x33>;
		status = "okay";
		st,wakeup-pin-number = <1>;
		st,notif-it-id = <0>;

		regulators {
			compatible = "st,stpmic1-regulators";
			buck1-supply = <&vin>;
			buck2-supply = <&vin>;
			buck3-supply = <&vin>;
			buck4-supply = <&vin>;
			ldo1-supply = <&vin>;
			ldo4-supply = <&vin>;
			ldo5-supply = <&vin>;
			ldo6-supply = <&vin>;
			vref_ddr-supply = <&vin>;
			pwr_sw1-supply = <&bst_out>;
			pwr_sw2-supply = <&v3v3_ao>;

			vddcpu: buck1 {
				regulator-name = "vddcpu";
				regulator-min-microvolt = <1250000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
				regulator-over-current-protection;

				lp-stop {
					regulator-suspend-microvolt = <1250000>;
				};
				lplv-stop {
					regulator-suspend-microvolt = <900000>;
				};
				lplv-stop2 {
					regulator-off-in-suspend;
				};
				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			vdd_ddr: buck2 {
				regulator-name = "vdd_ddr";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
				regulator-over-current-protection;

				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			vdd: buck3 {
				regulator-name = "vdd";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				st,mask-reset;
				regulator-over-current-protection;
			};

			vddcore: buck4 {
				regulator-name = "vddcore";
				regulator-min-microvolt = <1250000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
				regulator-over-current-protection;

				lplv-stop {
					regulator-suspend-microvolt = <900000>;
				};
				lplv-stop2 {
					regulator-suspend-microvolt = <900000>;
				};
				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			vdd_adc: ldo1 {
				regulator-name = "vdd_adc";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;

				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			unused1: ldo2 {
				regulator-name = "ldo2";
			};

			unused2: ldo3 {
				regulator-name = "ldo3";
			};

			vdd_usb: ldo4 {
				regulator-name = "vdd_usb";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;

				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			vdd_sd: ldo5 {
				regulator-name = "vdd_sd";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;

				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			v1v8_periph: ldo6 {
				regulator-name = "v1v8_periph";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;

				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			vref_ddr: vref_ddr {
				regulator-name = "vref_ddr";
				regulator-always-on;

				standby-ddr-sr {
					regulator-off-in-suspend;
				};
				standby-ddr-off {
					regulator-off-in-suspend;
				};
			};

			bst_out: boost {
				regulator-name = "bst_out";
			};

			v3v3_sw: pwr_sw2 {
				regulator-name = "v3v3_sw";
				regulator-active-discharge = <1>;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

&iwdg1 {
	timeout-sec = <32>;
	status = "okay";
};

&lptimer3 {
	status = "okay";

	counter {
		status = "okay";
	};
};

&ltdc {
	pinctrl-names = "default";
	pinctrl-0 = <&ltdc_pins_a>;
	status = "okay";
};

&oem_enc_key {
	st,non-secure-otp-provisioning;
};

&osc_calibration {
	csi-calibration {
		status = "okay";
	};

	hsi-calibration {
		status = "okay";
	};
};

&pka {
	status = "okay";
};

&pwr_irq {
	pinctrl-names = "default";
	pinctrl-0 = <&wakeup_pins>;
	status = "okay";
};

&pwr_regulators {
	system_suspend_supported_soc_modes = <
		STM32_PM_CSLEEP_RUN
		STM32_PM_CSTOP_ALLOW_LP_STOP
		STM32_PM_CSTOP_ALLOW_LPLV_STOP
		STM32_PM_CSTOP_ALLOW_LPLV_STOP2
		STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
	>;

	system_off_soc_mode = <STM32_PM_SHUTDOWN>;
	vdd-supply = <&vdd>;
	vdd_3v3_usbfs-supply = <&vdd_usb>;
};

&rcc {
	compatible = "st,stm32mp13-rcc", "syscon", "st,stm32mp13-rcc-mco";
	pinctrl-0 = <&rcc_mco_pins_a>;
	pinctrl-names = "default";

	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MLAHBS_PLL3
		CLK_RTC_LSE
		CLK_MCO1_HSE
		CLK_MCO2_DISABLED
		CLK_CKPER_HSE
		CLK_ETH1_PLL4P
		CLK_ETH2_PLL4P
		CLK_SDMMC1_PLL4P
		CLK_SDMMC2_PLL4P
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_I2C4_HSI
		CLK_I2C5_HSI
		CLK_USBO_USBPHY
		CLK_ADC2_CKPER
		CLK_I2C12_HSI
		CLK_UART1_HSI
		CLK_UART2_HSI
		CLK_UART35_HSI
		CLK_UART4_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SAES_AXI
		CLK_DCMIPP_PLL2Q
		CLK_LPTIM3_PCLK3
		CLK_RNG1_PLL4R
	>;

	st,clkdiv = <
		DIV(DIV_MPU, 1)
		DIV(DIV_AXI, 0)
		DIV(DIV_MLAHB, 0)
		DIV(DIV_APB1, 1)
		DIV(DIV_APB2, 1)
		DIV(DIV_APB3, 1)
		DIV(DIV_APB4, 1)
		DIV(DIV_APB5, 2)
		DIV(DIV_APB6, 1)
		DIV(DIV_RTC, 0)
		DIV(DIV_MCO1, 0)
		DIV(DIV_MCO2, 0)
	>;

	st,pll_vco {
		pll1_vco_2000Mhz: pll1-vco-2000Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <1 82>;
			frac = <0xAAA>;
		};

		pll1_vco_1300Mhz: pll1-vco-1300Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <2 80>;
			frac = <0x800>;
		};

		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <2 65>;
			frac = <0x1400>;
		};

		pll3_vco_417Mhz: pll3-vco-417Mhz {
			src = <CLK_PLL3_HSE>;
			divmn = <1 33>;
			frac = <0x1a04>;
		};

		pll4_vco_600Mhz: pll4-vco-600Mhz {
			src = <CLK_PLL4_HSE>;
			divmn = <1 49>;
		};
	};

	/* VCO = 1300.0 MHz => P = 650 (CPU) */
	pll1: st,pll@0 {
		compatible = "st,stm32mp1-pll";
		reg = <0>;

		st,pll = <&pll1_cfg1>;

		pll1_cfg1: pll1_cfg1 {
			st,pll_vco = <&pll1_vco_1300Mhz>;
			st,pll_div_pqr = <0 1 1>;
		};

		pll1_cfg2: pll1_cfg2 {
			st,pll_vco = <&pll1_vco_2000Mhz>;
			st,pll_div_pqr = <0 1 1>;
		};
	};

	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;

		st,pll = <&pll2_cfg1>;

		pll2_cfg1: pll2_cfg1 {
			st,pll_vco = <&pll2_vco_1066Mhz>;
			st,pll_div_pqr = <1 1 0>;
		};
	};

	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;

		st,pll = <&pll3_cfg1>;

		pll3_cfg1: pll3_cfg1 {
			st,pll_vco = <&pll3_vco_417Mhz>;
			st,pll_div_pqr = <1 16 36>;
		};
	};

	/* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		st,pll = <&pll4_cfg1>;

		pll4_cfg1: pll4_cfg1 {
			st,pll_vco = <&pll4_vco_600Mhz>;
			st,pll_div_pqr = <11 59 11>;
		};
	};

	st,clk_opp {
		/* CK_MPU clock config for MP13 */
		st,ck_mpu {

			cfg_1 {
				hz = <650000000>;
				st,clksrc = <CLK_MPU_PLL1P>;
				st,pll = <&pll1_cfg1>;
			};

			cfg_2 {
				hz = <1000000000>;
				st,clksrc = <CLK_MPU_PLL1P>;
				st,pll = <&pll1_cfg2>;
			};
		};
	};
};

&rng {
	status = "okay";
	clock-error-detect;
	st,rng-config = <RNG_CONFIG_NIST_B_ID>;
};

&rtc {
	status = "okay";
};

&saes {
	status = "okay";
};

&scmi_regu {
	scmi_vddcpu: voltd-vddcpu {
		reg = <VOLTD_SCMI_STPMIC1_BUCK1>;
		voltd-supply = <&vddcpu>;
	};
	scmi_vdd: voltd-vdd {
		reg = <VOLTD_SCMI_STPMIC1_BUCK3>;
		voltd-supply = <&vdd>;
	};
	scmi_vddcore: voltd-vddcore {
		reg = <VOLTD_SCMI_STPMIC1_BUCK4>;
		voltd-supply = <&vddcore>;
	};
	scmi_vdd_adc: voltd-vdd_adc {
		reg = <VOLTD_SCMI_STPMIC1_LDO1>;
		voltd-supply = <&vdd_adc>;
	};
	scmi_vdd_usb: voltd-vdd_usb {
		reg = <VOLTD_SCMI_STPMIC1_LDO4>;
		voltd-supply = <&vdd_usb>;
	};
	scmi_vdd_sd: voltd-vdd_sd {
		reg = <VOLTD_SCMI_STPMIC1_LDO5>;
		voltd-supply = <&vdd_sd>;
	};
	scmi_v1v8_periph: voltd-v1v8_periph {
		reg = <VOLTD_SCMI_STPMIC1_LDO6>;
		voltd-supply = <&v1v8_periph>;
	};
	scmi_v3v3_sw: voltd-v3v3_sw {
		reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
		voltd-supply = <&v3v3_sw>;
	};
};

&sdmmc1_io {
	vddsd1-supply = <&vdd>;
};

&sdmmc2_io {
	vddsd2-supply = <&vdd>;
};

&tamp {
	status = "okay";
	st,tamp_passive_nb_sample = <4>;
	st,tamp_passive_sample_clk_div = <16384>;

	tamp_passive@2 {
		pinctrl-0 = <&tamp0_in2_pin_a>;
		status = "okay";
	};

	/* Connect pin8 and pin22 from CN8 */
	tamp_active@1 {
		pinctrl-0 = <&tamp0_in3_pin_a &tamp0_out1_pin_a>;
		status = "disabled";
	};
};

&timers12 {
	status = "okay";

	counter {
		status = "okay";
	};
};

&tzc400 {
	memory-region = <&optee_framebuffer>;
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_a>;
	status = "okay";
};

&usart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usart1_pins_a>;
	uart-has-rtscts;
	status = "disabled";
};

&wakeup_pin_5 {
	bias-pull-up;
};