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A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.

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Name		Name	Last commit message	Last commit date
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Counter.v		Counter.v
README.md		README.md
RTC.v		RTC.v
SevenSeg.v		SevenSeg.v

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RealTimeClockModule

A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.

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A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.

simulation counters modelsim testbench verilog-hdl rtc-module seven-segment-display

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Verilog 100.0%