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setupppc.p
executable file
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setupppc.p
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# Copyright (c) 2015-2019 Dennis van der Boon
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
.include ppcdefines.i
.include sonnet_libppc.i
.include ppcmacros-std.i
.global PPCCode,PPCLen,ThisPPCProc,LIST_WAITINGTASKS,Init,ViolationAddress
.global MCPort,SysBase,PowerPCBase,DOSBase,sonnet_DebugLevel,sonnet_PosSize,PageTableSize
.global UtilityBase
.set PPCLen,(PPCEnd-PPCCode)
.set base_Comm,0
.set base_MemStart,4
.set base_MemLen,8
.set base_RTGBase,12
.set base_RTGLen,16
.set base_RTGType,20
.set base_RTGConfig,24
.set base_Options,28
.set base_XMPI,40
.set base_StartBAT,44
.set base_SizeBAT,48
.set rtgtype_ati,0x1002
.set rtgtype_voodoo3,0x121a
.set rtgtype_voodoo45,0x121b
#********************************************************************************************
.section "PPCSetup","acrx"
PPCCode: bl .SkipCom #0x3000 System initialization
.long 0 #Used for initial communication
.long 0 #MemStart
.long 0 #MemLen
.long 0 #RTGBase
.long 0 #RTGLen
.long 0 #RTGType
.long 0 #RTGConfig
.long 0 #Options1
.long 0 #Options2
.long 0 #Options3
.long 0 #XMPI Address
.long 0 #StartBAT
.long 0 #SizeBAT
.SkipCom: mflr r29 #For initial communication with 68k
lis r22,CMD_BASE@h #Used in setpcireg macro
mfpvr r25
rlwinm r25,r25,16,16,31
cmplwi r25,0x8000
bne .NoEIDIS
mfspr r25,MSSCR0
oris r25,r25,MSSCR0_EIDIS@h
mtspr MSSCR0,r25
.NoEIDIS: loadreg r0,'Init'
stw r0,base_Comm(r29)
bl Reset
lwz r25,base_XMPI(r29)
mr. r25,r25
bne .GoToClear
mfpvr r25
rlwinm r25,r25,16,16,31
cmplwi r25,ID_MPC834X
beq .GoToClear
b .SonnetStart
.GoToClear: li r3,0
li r4,63
mtctr r4
li r0,0
.ClearH: stwu r0,4(r3)
bdnz+ .ClearH
cmplwi r25,ID_MPC834X
beq .KillerStart
stw r25,XMPIBase(r0)
la r14,base_Options(r29)
li r8,0x13
stb r8,option_VersionNB(r14)
lwz r0,base_MemLen(r29)
stw r0,MemSize(r0)
bl .SetupHarFIFOs
bl Mpic
bl InstallExceptions
lwz r27,base_MemStart(r29)
stw r27,SonnetBase(r0)
lwz r8,base_MemLen(r29)
bl mmuSetup
loadreg r0,'Boon'
stw r0,0(r0)
b .SonSkip
#*********************************************************
.KillerStart: lwz r0,base_MemLen(r29)
stw r0,MemSize(r0)
bl .SetupKillerFIFOs
bl Ipic
bl InstallExceptions
lwz r27,base_MemStart(r29)
stw r27,SonnetBase(r0)
lwz r8,base_MemLen(r29)
bl mmuSetup
loadreg r0,'Boon'
stw r0,0(r0)
b .SonSkip
#*********************************************************
.SonnetStart: setpcireg PICR1 #Setup various PCI registers of the Sonnet
loadreg r25,VAL_PICR1
bl ConfigWrite32
setpcireg PICR2
loadreg r25,VAL_PICR2
bl ConfigWrite32
setpcireg PMCR1
loadreg r25,VAL_PMCR1
bl ConfigWrite16
setpcireg EUMBBAR
lis r25,EUMB@h
bl ConfigWrite32
la r14,base_Options(r29)
lbz r8,option_VersionNB(r14)
cmpwi r8,0x13
bne .NoForce
bl .DoForceMem
b .DoForce
.NoForce: bl ConfigMem #Result = Sonnet Mem Len in r8
.DoForce: bl InstallExceptions #Put exceptions in place
mr. r8,r8
beq .ErrorRam
lis r4,0x1000
cmplw r8,r4
ble .NoMaxRam2
mr r8,r4 #Limitations of Mediator without bank-switching
.NoMaxRam2: li r7,0
bl DirtyMemCheck
mr r28,r6
li r7,0
bl DirtyMemCheck
cmplw r28,r6
beq .PassedTest1
.MemUnstable: loadreg r0,'Err3'
b .Unstable
.PassedTest1: mr r7,r8
loadreg r6,0x100000
sub r7,r7,r6
mr r31,r7
bl DirtyMemCheck
mr r28,r6
mr r7,r31
bl DirtyMemCheck
cmplw r28,r6
beq .GotRam
b .MemUnstable
.ErrorRam: loadreg r0,'Err2'
.Unstable: stw r0,base_Comm(r29)
b .ErrorRam
.GotRam: mr r28,r8
lhz r3,base_RTGType(r29) #RTGType
cmpwi r3,rtgtype_ati #Check for ATI Gfx Card
beq .MaxRam
cmpwi r3,rtgtype_voodoo45 #Check for VooDoo4/5
bne .NoMaxRam
.MaxRam: lis r4,0x800 #Max 128MB RAM on Sonnet when ATI present
cmplw r8,r4
ble .NoMaxRam
mr r8,r4
.NoMaxRam: lis r27,0x8000 #Upper boundary PCI Memory Mediator
lwz r26,base_RTGBase(r29) #Get gfx mem (RTGBase)
cmplw r26,r27
blt .CheckJumper #Is Zorro3
mr r8,r28 #Restore full memory range
lis r27,0x9000 #Zorro2 plus 256MB ATI
cmplw r26,r27
beq .GotUpperLimit
lis r27,0x9800 #Zorro2 plus 128MB (or less) ATI
b .GotUpperLimit
.CheckJumper: rlwinm r26,r26,4,28,31
cmpwi r26,4
bne .NextCheck1
lis r27,0x6000 #Config jumper closed
b .GotUpperLimit
.NextCheck1: cmpwi r26,5
bne .NextCheck2
lis r27,0x5000
b .GotUpperLimit
.NextCheck2: cmpwi r26,3
bne .NextCheck3
lis r27,0x3000
mr r8,r28
b .GotUpperLimit
.NextCheck3: cmpwi r26,7
bne .GotUpperLimit
lis r27,0x7000
.GotUpperLimit: mr r26,r8
li r28,17
mtctr r28
li r28,1
li r25,29
Loop1: slw. r26,r26,r28
blt Fndbit
addi r25,r25,-1
bdnz Loop1
b Start #Error
Fndbit: slw. r26,r26,r28
beq SetLen
addi r25,r25,1
SetLen: mr r30,r28
slw r30,r30,r25
slw r30,r30,r28
subf r27,r30,r27
rlwinm. r0,r27,1,31,31
beq .UpperPCI
lis r27,0x1000
.UpperPCI: lis r26,EUMB@h
ori r26,r26,ITWR
stwbrx r25,0,r26 #Set size of Inbound Translate Window
sync
setpcireg LMBAR
mr r25,r27
ori r25,r25,8 #Set LMBAR to Base of memory plus size
bl ConfigWrite32
li r3,0
li r4,63
mtctr r4
li r0,0
.Clear0: stwu r0,4(r3)
bdnz+ .Clear0 #Clear first part of zero page
stw r8,MemSize(r0)
stw r27,base_MemStart(r29) #MemStart
stw r8,base_MemLen(r29) #MemLen
bl mmuSetup #Setup the Memory Management Unit
bl Epic #Setup the EPIC controller
.SonSkip: bl End
#*********************************************************
Start: #Dummy task at absolute (see ppcdefines)
nop
nop
b Start
#*********************************************************
End: mflr r4
li r14,0 #Reset
mtspr 285,r14 #Time Base Upper,
mtspr 284,r14 #Time Base Lower and
loadreg r28,0x7fffffff
mtdec r28 #Decrementer.
lwz r28,0(r0) #Get magic word
stw r28,base_Comm(r29) #Signal 68k that PPC is initialized
loadreg r6,'INIT'
.WInit: lwz r28,Init(r0)
cmplw r28,r6
bne .WInit
isync #Wait for 68k to set up library
loadreg r3,IdleTask #Start hardcoded at 0x8000
lwz r31,SonnetBase(r0)
add r3,r3,r31
loadreg r1,SysStack-0x20 #System stack in unused mem (See sonnet.s)
add r1,r1,r31
mr r31,r3
addi r5,r4,End-Start
subf r5,r4,r5
li r6,0
bl copy_and_flush #Put program in PPC Card Mem instead of PCI Mem
stw r13,-4(r1)
subi r13,r1,4
stwu r1,-288(r1)
lwz r3,PowerPCBase(r0)
la r4,LIST_READYTASKS(r3) #Set up various used lists
bl .MakeList
la r4,LIST_WAITINGTASKS(r3)
bl .MakeList
la r4,LIST_NEWTASKS(r3)
bl .MakeList
la r4,LIST_SEMAPHORES(r3)
bl .MakeList
la r4,LIST_PORTS(r3)
bl .MakeList
la r4,LIST_SNOOP(r3)
bl .MakeList
la r4,LIST_ALLTASKS(r3)
bl .MakeList
la r4,LIST_REMOVEDTASKS(r3)
bl .MakeList
la r4,LIST_REMOVEDEXC(r3)
bl .MakeList
la r4,LIST_READYEXC(r3)
bl .MakeList
la r4,LIST_INSTALLEDEXC(r3)
bl .MakeList
la r4,LIST_EXCMCHECK(r3)
bl .MakeList
la r4,LIST_EXCDACCESS(r3)
bl .MakeList
la r4,LIST_EXCIACCESS(r3)
bl .MakeList
la r4,LIST_EXCALIGN(r3)
bl .MakeList
la r4,LIST_EXCPROGRAM(r3)
bl .MakeList
la r4,LIST_EXCFPUN(r3)
bl .MakeList
la r4,LIST_EXCDECREMENTER(r3)
bl .MakeList
la r4,LIST_EXCSYSTEMCALL(r3)
bl .MakeList
la r4,LIST_EXCTRACE(r3)
bl .MakeList
la r4,LIST_EXCPERFMON(r3)
bl .MakeList
la r4,LIST_EXCIABR(r3)
bl .MakeList
la r4,LIST_EXCSYSMAN(r3)
bl .MakeList
la r4,LIST_EXCTHERMAN(r3)
bl .MakeList
la r4,LIST_EXCINTERRUPT(r3)
bl .MakeList
la r4,LIST_WAITTIME(r3)
bl .MakeList
la r4,LIST_MSGQUEUE(r3)
bl .MakeList
li r6,100 #Insert default values here
stw r6,IdDefTasks(r3)
stb r6,sonnet_AltivecOn(r3)
li r6,24
stb r6,BusyCounter(r3)
li r6,6000
stw r6,LowActivityPrio(r3) #Not used
lwz r6,SysBase(r0)
stw r6,sonnet_SysBase(r3)
lwz r6,DOSBase(r0)
stw r6,sonnet_DosBase(r3)
lwz r6,UtilityBase(r0)
stw r6,sonnet_UtilityBase(r3)
la r14,base_Options(r29)
lbz r6,option_EnDebug(r14)
stb r6,sonnet_DebugLevel(r3)
lbz r6,option_EnAlignExc(r14)
stb r6,sonnet_EnAlignExc(r3)
lbz r6,option_EnDAccessExc(r14)
stb r6,sonnet_EnDAccessExc(r3)
lbz r6,option_DisL2Flush(r14)
stb r6,DoDFlushAll(r3)
mfpvr r4
rlwinm r6,r4,16,16,31
cmplwi r6,ID_MPC834X
bne .NoKillerClock
loadreg r0,KillerQuantum
loadreg r4,KillerBusClock
lis r14,IMMR_ADDR_DEFAULT
addi r14,r14,IMMR_RCWLR
lwz r6,0(r14)
rlwinm. r6,r6,2,30,31
beq .PutClocks
rlwinm r0,r0,31,1,31
rlwinm r4,r4,31,1,31
b .PutClocks
.NoKillerClock: lbz r6,option_VersionNB(r14)
loadreg r0,SonnetQuantum
loadreg r4,SonnetBusClock
cmpwi r6,0x13
bne .PutClocks
loadreg r0,RaptureQuantum
loadreg r4,RaptureBusClock
.PutClocks: stw r0,Quantum(r0)
stw r0,sonnet_Quantum(r3)
stw r4,sonnet_BusClock(r3)
mr r14,r3
la r6,SemMemory(r14)
la r3,TaskListSem(r14)
mr r30,r3
mr r4,r3
stw r4,sonnet_TaskListSem(r14)
bl .InitSem
addi r4,r30,SSPPC_SIZE
stw r4,sonnet_SemListSem(r14)
addi r6,r6,32
bl .InitSem
addi r4,r30,SSPPC_SIZE*2
stw r4,sonnet_PortListSem(r14)
addi r6,r6,32
bl .InitSem
addi r4,r30,SSPPC_SIZE*3
stw r4,sonnet_SnoopSem(r14)
addi r6,r6,32
bl .InitSem
addi r4,r30,SSPPC_SIZE*4
stw r4,sonnet_MemSem(r14)
addi r6,r6,32
bl .InitSem
addi r4,r30,SSPPC_SIZE*5
stw r4,sonnet_WaitListSem(r14)
addi r6,r6,32
bl .InitSem
mfpvr r4
stw r4,sonnet_CPUInfo(r14)
lwz r4,MemSize(r0)
stw r4,sonnet_MemSize(r14)
lwz r4,MCPort(r0)
stw r4,sonnet_MCPort(r14)
lwz r4,SonnetBase(r0)
stw r4,sonnet_SonnetBase(r14)
mfpvr r4
rlwinm r4,r4,16,16,31
cmplwi r4,ID_MPC834X
beq .DidFIFOs
lwz r4,XMPIBase(r0)
mr. r4,r4
bne .DidFIFOs
bl .SetupMsgFIFOs
.DidFIFOs: lwz r14,PowerPCBase(r0)
lwz r4,_LVOSetCache+2(r14)
addi r6,r4,ViolationOS
stw r6,ViolationAddress(r0)
addi r6,r4,TaskStart
stw r6,RunPPCStart(r0)
addi r6,r4,ListStart
stw r6,AdListStart(r0)
addi r6,r4,ListEnd
stw r6,AdListEnd(r0)
addi r6,r4,TaskExit
stw r6,sonnet_TaskExitCode(r14)
addi r6,r4,NiceTable
stw r6,Table_NICE(r14) #NICE values are not used (yet).
bl Caches #Setup the L1 and L2 cache
mfpvr r3
rlwinm r3,r3,16,16,31
cmplwi r3,0x8000
bne .AutoDec
mfspr r3,HID0
oris r3,r3,HID0_TBEN@h #Enable TimeBase and Decrementer
mtspr HID0,r3
.AutoDec: li r3,0
loadreg r0,'REDY'
stw r0,Init(r0)
dcbf r0,r3
sync
lwz r3,PowerPCBase(r0)
mtsrr0 r31
loadreg r0,MACHINESTATE_DEFAULT
mtsrr1 r0 #load up user MSR. Also clears PSL_IP
lwz r0,Quantum(r0) #Load time slice
mtdec r0
rfi #To user code
#********************************************************************************************
.MakeList: stw r4,8(r4) #NewList()
lis r0,0
stwu r0,4(r4)
stw r4,-4(r4)
blr
.InitSem: addi r5,r4,SS_WAITQUEUE #InitSemaphore()
stw r5,8(r5)
li r0,0
stwu r0,4(r5)
stwu r5,-4(r5)
li r0,0
stw r0,SS_OWNER(r4)
sth r0,SS_NESTCOUNT(r4)
li r0,-1
sth r0,SS_QUEUECOUNT(r4)
stw r6,SSPPC_RESERVE(r4)
blr
#********************************************************************************************
.SetupMsgFIFOs: lis r14,EUMB@h
li r4,MUCR_CQS_FIFO4K #4K entries (16k x 4 FIFOs)
li r5,MUCR
stwbrx r4,r5,r14
sync
lwz r6,SonnetBase(r0)
lis r4,0x10
li r5,QBAR
stwbrx r4,r5,r14
sync
subi r4,r4,4
lis r5,0x20
add r5,r5,r6
li r6,4096
mr r7,r6
mtctr r6
.FillIBFL: stwu r5,4(r4)
addi r5,r5,192 #Message Frame Length
bdnz .FillIBFL
loadreg r4,(0x100000-4)+12*4096
mtctr r7
.FillOBFL: stwu r5,4(r4)
addi r5,r5,192
bdnz .FillOBFL
lis r14,EUMB@h
li r5,IFTPR
li r4,4096*0+4
stwbrx r4,r5,r14
sync
li r5,IFHPR
li r4,4096*0
stwbrx r4,r5,r14
sync
li r5,IPTPR
loadreg r4,4096*4
stwbrx r4,r5,r14
sync
li r5,IPHPR
loadreg r4,4096*4
stwbrx r4,r5,r14
sync
li r5,OPTPR
loadreg r4,4096*8
stwbrx r4,r5,r14
sync
li r5,OPHPR
loadreg r4,4096*8
stwbrx r4,r5,r14
sync
li r5,OFTPR
loadreg r4,4096*12+4
stwbrx r4,r5,r14
sync
li r5,OFHPR
loadreg r4,4096*12
stwbrx r4,r5,r14
sync
li r4,MUCR_CQS_FIFO4K|MUCR_CQE_ENABLE
li r5,MUCR
stwbrx r4,r5,r14
sync
blr
#********************************************************************************************
.SetupHarFIFOs:
lis r14,PPC_XCSR_BASE@h #Load Base XCSR
lwz r6,base_MemStart(r29)
lis r4,0x10
stw r4,XCSR_MIQB(r14) #MIQB on 0x100000
subi r4,r4,4
lis r5,0x20
add r5,r5,r6
li r6,4096
loadreg r20,(0x180000-4)
mtctr r6
loadreg r21,(0x140000-4)
addis r7,r5,0xc
loadreg r22,(0x1c0000-4)
li r23,0
.FillFIFO: stwu r5,4(r4)
stwu r7,4(r20)
stwu r23,4(r21)
stwu r23,4(r22)
addi r5,r5,192 #Message Frame Length
addi r7,r7,192
bdnz .FillFIFO
li r4,4
stw r4,XCSR_MIIFT(r14)
li r4,0
stw r4,XCSR_MIIFH(r14)
lis r4,4
stw r4,XCSR_MIIPT(r14)
lis r4,4
stw r4,XCSR_MIIPH(r14)
loadreg r4,0x80004 #Each FIFO (MIIF, MIIP, MIOF, MIOP) sits on a 256k boundary
stw r4,XCSR_MIOFT(r14)
lis r4,8
stw r4,XCSR_MIOFH(r14)
lis r4,12
stw r4,XCSR_MIOPT(r14)
lis r4,12
stw r4,XCSR_MIOPH(r14)
lis r4,(XCSR_MICT_ENA|XCSR_MICT_QSZ_16K)@h
stw r4,XCSR_MICT(r14) #enable 4k entries x 4 bytes address = 16k per FIFO
sync #Is it safer to clear the empty FIFOs?
blr
#********************************************************************************************
.SetupKillerFIFOs:
lwz r6,base_MemStart(r29)
lis r4,0x38
subi r4,r4,4
lis r5,0x20
add r5,r5,r6 #Sonnetbase + 200000: Messages
li r6,4096
loadreg r20,(0x3a0000-4)
mtctr r6
loadreg r21,(0x390000-4)
addis r7,r5,0xc
loadreg r22,(0x3b0000-4)
li r23,0
.FillKillFIFO: stwu r5,4(r4)
stwu r7,4(r20)
stwu r23,4(r21)
stwu r23,4(r22)
addi r5,r5,192 #Message Frame Length
addi r7,r7,192
bdnz .FillKillFIFO
lwz r6,base_MemStart(r29)
addis r6,r6,0x38
lis r23,FIFO_BASE
addi r4,r6,4
stw r4,FIFO_MIIFT(r23)
mr r4,r6
stw r4,FIFO_MIIFH(r23)
addis r4,r6,1
stw r4,FIFO_MIIPT(r23)
stw r4,FIFO_MIIPH(r23)
addis r4,r6,2
stw r4,FIFO_MIOFH(r23)
addi r4,r4,4
stw r4,FIFO_MIOFT(r23)
addis r4,r6,3
stw r4,FIFO_MIOPT(r23)
stw r4,FIFO_MIOPH(r23)
blr
#********************************************************************************************
Reset: mflr r15
mfmsr r1
andi. r1,r1,PSL_IP
mtmsr r1 #Clear MSR, keep Interrupt Prefix for now
isync
#Zero-out registers
li r0,0
mtsprg0 r0
mtsprg1 r0
mtsprg2 r0
mtsprg3 r0
loadreg r3,HID0_NHR #Set HID0 to known state
mfspr r4,HID0
and r3,r4, r3 #Clear other bits
mtspr HID0,r3
sync
loadreg r3,PSL_FP #Set MPU/MSR to a known state. Turn on FP
or r3,r1,r3
mtmsr r3
isync
#Init the floating point control/status register
mtfsfi 7,0
mtfsfi 6,0
mtfsfi 5,0
mtfsfi 4,0
mtfsfi 3,0
mtfsfi 2,0
mtfsfi 1,0
mtfsfi 0,0
isync
#Initialize floating point data regs to known state
bl ifpdr_value
.long 0x3f800000 #Value of 1.0
ifpdr_value: mflr r3
lfs f0,0(r3)
lfs f1,0(r3)
lfs f2,0(r3)
lfs f3,0(r3)
lfs f4,0(r3)
lfs f5,0(r3)
lfs f6,0(r3)
lfs f7,0(r3)
lfs f8,0(r3)
lfs f9,0(r3)
lfs f10,0(r3)
lfs f11,0(r3)
lfs f12,0(r3)
lfs f13,0(r3)
lfs f14,0(r3)
lfs f15,0(r3)
lfs f16,0(r3)
lfs f17,0(r3)
lfs f18,0(r3)
lfs f19,0(r3)
lfs f20,0(r3)
lfs f21,0(r3)
lfs f22,0(r3)
lfs f23,0(r3)
lfs f24,0(r3)
lfs f25,0(r3)
lfs f26,0(r3)
lfs f27,0(r3)
lfs f28,0(r3)
lfs f29,0(r3)
lfs f30,0(r3)
lfs f31,0(r3)
sync
#Clear BAT and Segment mapping registers
li r1,0
mtspr ibat0u,r1
mtspr ibat1u,r1
mtspr ibat2u,r1
mtspr ibat3u,r1
mtspr ibat0l,r1
mtspr ibat1l,r1
mtspr ibat2l,r1
mtspr ibat3l,r1
mtspr dbat0u,r1
mtspr dbat1u,r1
mtspr dbat2u,r1
mtspr dbat3u,r1
mtspr dbat0l,r1
mtspr dbat1l,r1
mtspr dbat2l,r1
mtspr dbat3l,r1
mfpvr r4
rlwinm r3,r4,16,16,31
cmplwi r3,0x8083
beq .ExtraBats
rlwinm r3,r4,8,24,31
cmpwi r3,0x70
bne .SkipExtraBats
.ExtraBats: mtspr ibat4u,r1
mtspr ibat5u,r1
mtspr ibat6u,r1
mtspr ibat7u,r1
mtspr ibat4l,r1
mtspr ibat5l,r1
mtspr ibat6l,r1
mtspr ibat7l,r1
mtspr dbat4u,r1
mtspr dbat5u,r1
mtspr dbat6u,r1
mtspr dbat7u,r1
mtspr dbat4l,r1
mtspr dbat5l,r1
mtspr dbat6l,r1
mtspr dbat7l,r1
.SkipExtraBats: isync
sync
sync
mtsr 0,r1
mtsr 1,r1
mtsr 2,r1
mtsr 3,r1
mtsr 4,r1
mtsr 5,r1
mtsr 6,r1
mtsr 7,r1
mtsr 8,r1
mtsr 9,r1
mtsr 10,r1
mtsr 11,r1
mtsr 12,r1
mtsr 13,r1
mtsr 14,r1
mtsr 15,r1
isync
sync
sync
mtlr r15
blr
#********************************************************************************************
Epic: lis r26,EUMB@h
loadreg r27,EPIC_GCR
add r27,r26,r27
li r28,0xa0
stw r28,0(r27) #Reset EPIC
.ResLoop: lwz r28,0(r27)
andi. r28,r28,0x80
bne .ResLoop #Wait for reset
li r28,0x20
stw r28,0(r27) #Set Mixed Mode
loadreg r28,0x80050042
loadreg r27,EPIC_IIVPR3
add r27,r26,r27
stwbrx r28,0,r27 #Set MU interrupt, Pri = 5, Vector = 0x42
sync
loadreg r27,EPIC_EICR
add r27,r26,r27
lwz r28,0(r27)
rlwinm r28,r28,0,21,19 #Doc says Set SIE = 0
stw r28,0(r27)
loadreg r27,EPIC_IIVPR3
add r27,r26,r27
lwz r28,0(r27)
rlwinm r28,r28,0,25,23 #Doc says Mask M bit now. Can maybe already at
stw r28,0(r27) #while setting the interrupt above?