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Convert to Verilog2001, thanks Magnus Karlsson
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@SaucySoliton
SaucySoliton committed Jul 8, 2017
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40 changes: 21 additions & 19 deletions HDL/cog_alu.v
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Expand Up @@ -21,6 +21,8 @@ the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/

// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style

module cog_alu
(
input [5:0] i,
Expand Down Expand Up @@ -48,16 +50,16 @@ wire [31:0] dr = { d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7],
d[16], d[17], d[18], d[19], d[20], d[21], d[22], d[23],
d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31] };

wire [7:0][30:0] ri = { 31'b0, // rev
{31{d[31]}}, // sar
{31{ci}}, // rcl
{31{ci}}, // rcr
31'b0, // shl
31'b0, // shr
dr[30:0], // rol
d[30:0] }; // ror
wire [255:0] ri = { 32'b0, // rev
{32{d[31]}}, // sar
{32{ci}}, // rcl
{32{ci}}, // rcr
32'b0, // shl
32'b0, // shr
dr[31:0], // rol
d[31:0] }; // ror

wire [62:0] rot = {ri[i[2:0]], i[0] ? dr : d} >> s[4:0];
wire [63:0] rot = {ri[i[2:0]*32 +: 32], i[0] ? dr : d} >> s[4:0];

wire [31:0] rotr = { rot[0], rot[1], rot[2], rot[3], rot[4], rot[5], rot[6], rot[7],
rot[8], rot[9], rot[10], rot[11], rot[12], rot[13], rot[14], rot[15],
Expand All @@ -74,18 +76,18 @@ wire rot_c = ~&i[2:1] && i[0] ? dr[0] : d[0];
wire [1:0] log_s = i[2] ? {(i[1] ? zi : ci) ^ i[0], 1'b0} // muxc/muxnc/muxz/muxnz
: {i[1], ~^i[1:0]}; // and/andn/or/xor

wire [3:0][31:0] log_x = { d ^ s, // 11 = xor
d | s, // 10 = or mux 1
d & s, // 01 = and
d & ~s }; // 00 = andn mux 0
wire [127:0] log_x = { d ^ s, // 11 = xor
d | s, // 10 = or mux 1
d & s, // 01 = and
d & ~s }; // 00 = andn mux 0

wire [3:0][31:0] mov_x = { d[31:9], p, // jmpret
s[8:0], d[22:0], // movi
d[31:18], s[8:0], d[8:0], // movd
d[31:9], s[8:0] }; // movs
wire [127:0] mov_x = { d[31:9], p, // jmpret
s[8:0], d[22:0], // movi
d[31:18], s[8:0], d[8:0], // movd
d[31:9], s[8:0] }; // movs

wire [31:0] log_r = i[3] ? log_x[log_s] // and/andn/or/xor/muxc/muxnc/muxz/muxnz
: i[2] ? mov_x[i[1:0]] // movs/movd/movi/jmpret
wire [31:0] log_r = i[3] ? log_x[log_s*32 +: 32] // and/andn/or/xor/muxc/muxnc/muxz/muxnz
: i[2] ? mov_x[i[1:0]*32 +: 32] // movs/movd/movi/jmpret
: s; // mins/maxs/min/max

wire log_c = ^log_r; // c is parity of result
Expand Down
38 changes: 20 additions & 18 deletions HDL/cog_ctr.v
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Expand Up @@ -21,6 +21,8 @@ the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/

// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style

module cog_ctr
(
input clk_cog,
Expand Down Expand Up @@ -71,26 +73,26 @@ if (|ctr[30:29])

// trigger, outputs, phase

// trigger outb outa
wire [15:0][2:0] tp = { dly == 2'b10, !dly[0], 1'b0, // neg edge w/feedback
dly == 2'b10, 1'b0, 1'b0, // neg edge
!dly[0], !dly[0], 1'b0, // neg w/feedback
!dly[0], 1'b0, 1'b0, // neg
dly == 2'b01, !dly[0], 1'b0, // pos edge w/feedback
dly == 2'b01, 1'b0, 1'b0, // pos edge
dly[0], !dly[0], 1'b0, // pos w/feedback
dly[0], 1'b0, 1'b0, // pos
1'b1, !phs[32], phs[32], // duty differential
1'b1, 1'b0, phs[32], // duty single
1'b1, !phs[31], phs[31], // nco differential
1'b1, 1'b0, phs[31], // nco single
1'b1, !pll, pll, // pll differential
1'b1, 1'b0, pll, // pll single
1'b1, 1'b0, 1'b0, // pll internal
1'b0, 1'b0, 1'b0 }; // off
// trigger outb outa
wire [63:0] tp = { 1'b0, dly == 2'b10, !dly[0], 1'b0, // neg edge w/feedback
1'b0, dly == 2'b10, 1'b0, 1'b0, // neg edge
1'b0, !dly[0], !dly[0], 1'b0, // neg w/feedback
1'b0, !dly[0], 1'b0, 1'b0, // neg
1'b0, dly == 2'b01, !dly[0], 1'b0, // pos edge w/feedback
1'b0, dly == 2'b01, 1'b0, 1'b0, // pos edge
1'b0, dly[0], !dly[0], 1'b0, // pos w/feedback
1'b0, dly[0], 1'b0, 1'b0, // pos
1'b0, 1'b1, !phs[32], phs[32], // duty differential
1'b0, 1'b1, 1'b0, phs[32], // duty single
1'b0, 1'b1, !phs[31], phs[31], // nco differential
1'b0, 1'b1, 1'b0, phs[31], // nco single
1'b0, 1'b1, !pll, pll, // pll differential
1'b0, 1'b1, 1'b0, pll, // pll single
1'b0, 1'b1, 1'b0, 1'b0, // pll internal
1'b0, 1'b0, 1'b0, 1'b0 }; // off

wire [3:0] pick = ctr[29:26];
wire [2:0] tba = tp[pick];
wire [2:0] tba = tp[pick*4 +: 3];

wire trig = ctr[30] ? pick[dly] : tba[2]; // trigger
wire outb = ctr[30] ? 1'b0 : tba[1]; // outb
Expand Down
6 changes: 4 additions & 2 deletions HDL/cog_vid.v
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Expand Up @@ -21,6 +21,8 @@ the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/

// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style

module cog_vid
(
input clk_cog,
Expand Down Expand Up @@ -178,9 +180,9 @@ reg [2:0] composite;
always @(posedge vclk)
composite <= vid[27] ? colormod : discrete[2:0];

wire [15:0][2:0] level = 48'b011_100_100_101_101_110_110_111_011_011_010_010_001_001_000_000;
wire [63:0] level = 64'b0011_0100_0100_0101_0101_0110_0110_0111_0011_0011_0010_0010_0001_0001_0000_0000;

wire [3:0] broadcast = {carrier ^ aural[vid[25:23]], level[{carrier, composite}]};
wire [3:0] broadcast = {carrier ^ aural[vid[25:23]], level[{carrier, composite}*4 +: 3]};


// output pins
Expand Down
10 changes: 5 additions & 5 deletions HDL/dig.v
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Expand Up @@ -79,15 +79,15 @@ else if (ena_bus)
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [1:0] bus_s [7:0];
wire [15:0] bus_a [7:0];
wire [31:0] bus_d [7:0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
wire [31:0] outx [7:0];
wire [31:0] dirx [7:0];
wire [7:0] ptr_w;
wire [27:0] ptr_d;
wire [7:0] cog_ena;
Expand Down
7 changes: 4 additions & 3 deletions readme.md
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Expand Up @@ -4,22 +4,23 @@ Propeller 1 Design

About this Repository
---------------------
* Support for simulation in Verilator
* Propeller simulation powered by Verilator
* Virtual EEPROM attached to simulation
* Single ROM file
* Configurable RAM and ROM size in features.v
* Hub ram is pre-loaded with EEPROM contents
* Custom booter checks hub ram for a pre-loaded program
* Booter is pre-loaded into cog ram
* Uses Verilog2001 instead of SystemVerilog

Note about pre-loaded RAM: The RAM contents are likely not reset by inp_resn. It is assumed that the simulator is reset once at the start. Repeated resets may have result in unexpected behavior. FPGAs might need to be reconfigured to reset ram contents.

Note about RAM options: The original booter seems to load 32kB from EEPROM, overwriting data if hub<32kB. This is not yet fixed in the custom booter.

Possible future work:
* Convert to verilog 2001, needed for icestorm
* Build for iCE40 HX8K using icestorm (currently not functional)
* Reduce ROM by pre-loading booter into cog RAM

* load .binary/EEPROM file directly from main.cpp


P8X32A Emulation on FPGA Boards
Expand Down

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