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[ASAN][AMDGPU] NFC. Improve instrumentation tests. (llvm#73919)
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* Added 128 bit wide operation tests (fast path check).
* Added test for recovery mode.

Upcoming patch llvm#72247.
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@vpykhtin
vpykhtin committed Dec 1, 2023
1 parent 668a4a2 commit 8123fd9
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74 changes: 72 additions & 2 deletions llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt < %s -passes=asan -S | FileCheck %s
; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
target triple = "amdgcn-amd-amdhsa"

@x = addrspace(4) global [2 x i32] zeroinitializer, align 4
@x8 = addrspace(4) global [2 x i64] zeroinitializer, align 8

define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
; CHECK-LABEL: define protected amdgpu_kernel void @constant_load(
Expand All @@ -16,7 +18,7 @@ define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF1:![0-9]+]]
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF2:![0-9]+]]
; CHECK: 6:
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
Expand All @@ -30,9 +32,77 @@ define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4
; CHECK-NEXT: ret void
;
; RECOV-LABEL: define protected amdgpu_kernel void @constant_load(
; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
; RECOV-NEXT: entry:
; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]]
; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF2:![0-9]+]]
; RECOV: 6:
; RECOV-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
; RECOV-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
; RECOV-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
; RECOV-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
; RECOV: 11:
; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP0]]) #[[ATTR3:[0-9]+]]
; RECOV-NEXT: br label [[TMP12]]
; RECOV: 12:
; RECOV-NEXT: br label [[TMP13]]
; RECOV: 13:
; RECOV-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4
; RECOV-NEXT: ret void
;
entry:

%a = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 %i
%q = load i32, ptr addrspace(4) %a, align 4
ret void
}

define protected amdgpu_kernel void @constant_load_8(i64 %i) sanitize_address {
; CHECK-LABEL: define protected amdgpu_kernel void @constant_load_8(
; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]]
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]]
; CHECK: 6:
; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP0]]) #[[ATTR3]]
; CHECK-NEXT: unreachable
; CHECK: 7:
; CHECK-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8
; CHECK-NEXT: ret void
;
; RECOV-LABEL: define protected amdgpu_kernel void @constant_load_8(
; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0]] {
; RECOV-NEXT: entry:
; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]]
; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]]
; RECOV: 6:
; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP0]]) #[[ATTR3]]
; RECOV-NEXT: br label [[TMP7]]
; RECOV: 7:
; RECOV-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8
; RECOV-NEXT: ret void
;
entry:
%a = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 %i
%q = load i64, ptr addrspace(4) %a, align 8
ret void
}
187 changes: 187 additions & 0 deletions llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt < %s -passes=asan -S | FileCheck %s
; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
target triple = "amdgcn-amd-amdhsa"

Expand Down Expand Up @@ -36,6 +37,40 @@ define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i)
; CHECK-NEXT: store i32 0, ptr [[Q]], align 4
; CHECK-NEXT: ret void
;
; RECOV-LABEL: define protected amdgpu_kernel void @generic_store(
; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
; RECOV-NEXT: entry:
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP19:%.*]]
; RECOV: 4:
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
; RECOV: 11:
; RECOV-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7
; RECOV-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3
; RECOV-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
; RECOV-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
; RECOV-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17:%.*]]
; RECOV: 16:
; RECOV-NEXT: call void @__asan_report_store4_noabort(i64 [[TMP5]]) #[[ATTR3:[0-9]+]]
; RECOV-NEXT: br label [[TMP17]]
; RECOV: 17:
; RECOV-NEXT: br label [[TMP18]]
; RECOV: 18:
; RECOV-NEXT: br label [[TMP19]]
; RECOV: 19:
; RECOV-NEXT: store i32 0, ptr [[Q]], align 4
; RECOV-NEXT: ret void
;
entry:

%q = addrspacecast ptr addrspace(1) %p to ptr
Expand Down Expand Up @@ -76,9 +111,161 @@ define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) s
; CHECK-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4
; CHECK-NEXT: ret void
;
; RECOV-LABEL: define protected amdgpu_kernel void @generic_load(
; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
; RECOV-NEXT: entry:
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP19:%.*]]
; RECOV: 4:
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF0]]
; RECOV: 11:
; RECOV-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7
; RECOV-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3
; RECOV-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
; RECOV-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
; RECOV-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17:%.*]]
; RECOV: 16:
; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP5]]) #[[ATTR3]]
; RECOV-NEXT: br label [[TMP17]]
; RECOV: 17:
; RECOV-NEXT: br label [[TMP18]]
; RECOV: 18:
; RECOV-NEXT: br label [[TMP19]]
; RECOV: 19:
; RECOV-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4
; RECOV-NEXT: ret void
;
entry:

%q = addrspacecast ptr addrspace(1) %p to ptr
%r = load i32, ptr %q, align 4
ret void
}

define protected amdgpu_kernel void @generic_store_8(ptr addrspace(1) %p) sanitize_address {
; CHECK-LABEL: define protected amdgpu_kernel void @generic_store_8(
; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
; CHECK: 4:
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
; CHECK: 11:
; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP5]]) #[[ATTR3]]
; CHECK-NEXT: unreachable
; CHECK: 12:
; CHECK-NEXT: br label [[TMP13]]
; CHECK: 13:
; CHECK-NEXT: store i64 0, ptr [[Q]], align 8
; CHECK-NEXT: ret void
;
; RECOV-LABEL: define protected amdgpu_kernel void @generic_store_8(
; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
; RECOV-NEXT: entry:
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
; RECOV: 4:
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
; RECOV: 11:
; RECOV-NEXT: call void @__asan_report_store8_noabort(i64 [[TMP5]]) #[[ATTR3]]
; RECOV-NEXT: br label [[TMP12]]
; RECOV: 12:
; RECOV-NEXT: br label [[TMP13]]
; RECOV: 13:
; RECOV-NEXT: store i64 0, ptr [[Q]], align 8
; RECOV-NEXT: ret void
;
entry:
%q = addrspacecast ptr addrspace(1) %p to ptr
store i64 0, ptr %q, align 8
ret void
}

define protected amdgpu_kernel void @generic_load_8(ptr addrspace(1) %p) sanitize_address {
; CHECK-LABEL: define protected amdgpu_kernel void @generic_load_8(
; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
; CHECK: 4:
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
; CHECK: 11:
; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP5]]) #[[ATTR3]]
; CHECK-NEXT: unreachable
; CHECK: 12:
; CHECK-NEXT: br label [[TMP13]]
; CHECK: 13:
; CHECK-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8
; CHECK-NEXT: ret void
;
; RECOV-LABEL: define protected amdgpu_kernel void @generic_load_8(
; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
; RECOV-NEXT: entry:
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
; RECOV: 4:
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
; RECOV: 11:
; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP5]]) #[[ATTR3]]
; RECOV-NEXT: br label [[TMP12]]
; RECOV: 12:
; RECOV-NEXT: br label [[TMP13]]
; RECOV: 13:
; RECOV-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8
; RECOV-NEXT: ret void
;
entry:
%q = addrspacecast ptr addrspace(1) %p to ptr
%r = load i64, ptr %q, align 8
ret void
}
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