GitHub - Shreefmohamed303/DMA: DMA Hardware Description with Verilog

Shreefmohamed303 / DMA Public

forked from AmrElsersy/DMA

DMA Hardware Description with Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
work		work
Command_Register.v		Command_Register.v
Command_Register.v.bak		Command_Register.v.bak
Computer_architecture.v		Computer_architecture.v
Computer_architecture.v.bak		Computer_architecture.v.bak
DMA.cr.mti		DMA.cr.mti
DMA.mpf		DMA.mpf
DMA.v		DMA.v
DMA.v.bak		DMA.v.bak
Data_buffer.v		Data_buffer.v
Data_buffer.v.bak		Data_buffer.v.bak
Decoder_2to4.v		Decoder_2to4.v
IO_Device.v		IO_Device.v
IO_Device.v.bak		IO_Device.v.bak
InputOutput_Buffer.v		InputOutput_Buffer.v
MIPS.v		MIPS.v
MIPS.v.bak		MIPS.v.bak
MRCommand.v		MRCommand.v
Mode_register.v		Mode_register.v
Mode_register.v.bak		Mode_register.v.bak
PeriorityEncoder.v		PeriorityEncoder.v
PeriorityEncoder.v.bak		PeriorityEncoder.v.bak
RAM.v		RAM.v
ReadBuffer_RW_Bus.v		ReadBuffer_RW_Bus.v
ReadWrite_buffer.v		ReadWrite_buffer.v
ReadWrite_buffer.v.bak		ReadWrite_buffer.v.bak
Read_Buffer.v		Read_Buffer.v
Read_buffer_current.v		Read_buffer_current.v
Read_buffer_reg.v		Read_buffer_reg.v
Request_Register.v		Request_Register.v
Status_register.v		Status_register.v
Untitled.png		Untitled.png
feedback.txt		feedback.txt
ins.txt		ins.txt
io_buffer.v		io_buffer.v
output_buffer.v		output_buffer.v
ray2.cr.mti		ray2.cr.mti
ray2.mpf		ray2.mpf
temporary_register.v		temporary_register.v
timing_control.v		timing_control.v
timing_control.v.bak		timing_control.v.bak
transcript		transcript
vsim.wlf		vsim.wlf
write_buffer.v		write_buffer.v