ADD: Split bus tests for bus- and sbus-based GPIO modules

tests/test_SimGpio.py

@@ -55,8 +55,13 @@
 
 
 class TestSimGpio(unittest.TestCase):
+    def __init__(self, testname, tb='test_SimGpio.v', bus='basil.utils.sim.BasilBusDriver'):
+        super(TestSimGpio, self).__init__(testname)
+        self._test_tb = tb
+        self._sim_bus = bus
+
     def setUp(self):
-        cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimGpio.v')])
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()

tests/test_SimGpio_sbus.py

@@ -0,0 +1,27 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+import unittest
+import sys
+
+from tests.test_SimGpio import TestSimGpio
+
+
+if __name__ == '__main__':
+    # https://stackoverflow.com/a/2081750
+    test_loader = unittest.TestLoader()
+    test_names = test_loader.getTestCaseNames(TestSimGpio)
+
+    suite = unittest.TestSuite()
+
+    for test_name in test_names:
+        suite.addTest(TestSimGpio(test_name, 'test_SimGpio_sbus.v', 'basil.utils.sim.BasilSbusDriver'))
+    for test_name in test_names:
+        suite.addTest(TestSimGpio(test_name, 'test_SimGpio_sbus_top.v', 'basil.utils.sim.BasilSbusDriver'))
+
+    result = unittest.TextTestRunner().run(suite)
+    sys.exit(not result.wasSuccessful())

tests/test_SimGpio_sbus.v

@@ -0,0 +1,84 @@
+/**
+ * ------------------------------------------------------------
+ * Copyright (c) All rights reserved
+ * SiLab, Institute of Physics, University of Bonn
+ * ------------------------------------------------------------
+ */
+
+`timescale 1ps / 1ps
+
+`include "utils/sbus_to_ip.v"
+`include "gpio/gpio_core.v"
+`include "gpio/gpio_sbus.v"
+
+module tb (
+    input wire          BUS_CLK,
+    input wire          BUS_RST,
+    input wire  [15:0]  BUS_ADD,
+    input wire  [7:0]   BUS_DATA_IN,
+    output wire [7:0]   BUS_DATA_OUT,
+    input wire          BUS_RD,
+    input wire          BUS_WR
+);
+
+localparam GPIO_BASEADDR = 16'h0000;
+localparam GPIO_HIGHADDR = 16'h000f;
+
+localparam GPIO2_BASEADDR = 16'h0010;
+localparam GPIO2_HIGHADDR = 16'h001f;
+
+wire [7:0] BUS_DATA_OUT_1;
+wire [7:0] BUS_DATA_OUT_2;
+
+assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2;
+
+// FIXME: hack for Verilator optimization error
+/* verilator lint_off UNOPT */
+wire [23:0] IO;
+
+assign IO[15:8] = IO[7:0];
+assign IO[23:20] = IO[19:16];
+/* verilator lint_on UNOPT */
+
+gpio_sbus #(
+    .BASEADDR(GPIO_BASEADDR),
+    .HIGHADDR(GPIO_HIGHADDR),
+    .IO_WIDTH(24),
+    .IO_DIRECTION(24'h0000ff),
+    .IO_TRI(24'hff0000)
+) i_gpio (
+    .BUS_CLK(BUS_CLK),
+    .BUS_RST(BUS_RST),
+    .BUS_ADD(BUS_ADD),
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1),
+    .BUS_RD(BUS_RD),
+    .BUS_WR(BUS_WR),
+    .IO(IO)
+);
+
+wire [15:0] IO_2;
+assign IO_2 = 16'ha5cd;
+
+gpio_sbus #(
+    .BASEADDR(GPIO2_BASEADDR),
+    .HIGHADDR(GPIO2_HIGHADDR),
+    .IO_WIDTH(16),
+    .IO_DIRECTION(16'h0000)
+) i_gpio2 (
+    .BUS_CLK(BUS_CLK),
+    .BUS_RST(BUS_RST),
+    .BUS_ADD(BUS_ADD),
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_2),
+    .BUS_RD(BUS_RD),
+    .BUS_WR(BUS_WR),
+    .IO(IO_2)
+);
+
+initial begin
+    $dumpfile("gpio_sbus1.vcd");
+    $dumpvars(0);
+end
+
+endmodule

tests/test_SimGpio_sbus_top.v

@@ -0,0 +1,82 @@
+/**
+ * ------------------------------------------------------------
+ * Copyright (c) All rights reserved
+ * SiLab, Institute of Physics, University of Bonn
+ * ------------------------------------------------------------
+ */
+
+`timescale 1ps / 1ps
+
+`include "utils/bus_to_ip.v"
+`include "gpio/gpio_core.v"
+`include "gpio/gpio.v"
+
+module tb (
+    input wire          BUS_CLK,
+    input wire          BUS_RST,
+    input wire  [15:0]  BUS_ADD,
+    input wire  [7:0]   BUS_DATA_IN,
+    output wire [7:0]   BUS_DATA_OUT,
+    input wire          BUS_RD,
+    input wire          BUS_WR
+);
+
+localparam GPIO_BASEADDR = 16'h0000;
+localparam GPIO_HIGHADDR = 16'h000f;
+
+localparam GPIO2_BASEADDR = 16'h0010;
+localparam GPIO2_HIGHADDR = 16'h001f;
+
+// Connect tb internal bus to external split bus
+wire [7:0] BUS_DATA;
+assign BUS_DATA = BUS_DATA_IN;
+assign BUS_DATA_OUT = BUS_DATA;
+
+// FIXME: hack for Verilator optimization error
+/* verilator lint_off UNOPT */
+wire [23:0] IO;
+
+assign IO[15:8] = IO[7:0];
+assign IO[23:20] = IO[19:16];
+/* verilator lint_on UNOPT */
+
+gpio #(
+    .BASEADDR(GPIO_BASEADDR),
+    .HIGHADDR(GPIO_HIGHADDR),
+    .IO_WIDTH(24),
+    .IO_DIRECTION(24'h0000ff),
+    .IO_TRI(24'hff0000)
+) i_gpio (
+    .BUS_CLK(BUS_CLK),
+    .BUS_RST(BUS_RST),
+    .BUS_ADD(BUS_ADD),
+    .BUS_DATA(BUS_DATA),
+    .BUS_RD(BUS_RD),
+    .BUS_WR(BUS_WR),
+    .IO(IO)
+);
+
+wire [15:0] IO_2;
+assign IO_2 = 16'ha5cd;
+
+gpio #(
+    .BASEADDR(GPIO2_BASEADDR),
+    .HIGHADDR(GPIO2_HIGHADDR),
+    .IO_WIDTH(16),
+    .IO_DIRECTION(16'h0000)
+) i_gpio2 (
+    .BUS_CLK(BUS_CLK),
+    .BUS_RST(BUS_RST),
+    .BUS_ADD(BUS_ADD),
+    .BUS_DATA(BUS_DATA),
+    .BUS_RD(BUS_RD),
+    .BUS_WR(BUS_WR),
+    .IO(IO_2)
+);
+
+initial begin
+    $dumpfile("gpio_sbus2.vcd");
+    $dumpvars(0);
+end
+
+endmodule