ADD: Fifo8to32 top-split bus test

tests/test_SimFifo8to32.py

@@ -29,9 +29,20 @@
 """
 
 
-class TestSimM26(unittest.TestCase):
+class TestSimFifo8to32(unittest.TestCase):
+    def __init__(self, testname, tb='test_SimFifo8to32.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
+        super(TestSimFifo8to32, self).__init__(testname)
+        self._test_tb = tb
+        self._sim_bus = bus_drv
+        self._bus_split_def = ()
+        if bus_split is not False:
+            if bus_split == 'sbus':
+                self._bus_split_def = ("BASIL_SBUS",)
+            elif bus_split == 'top':
+                self._bus_split_def = ("BASIL_TOPSBUS",)
+
     def setUp(self):
-        cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimFifo8to32.v')])
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()

tests/test_SimFifo8to32.v

@@ -7,6 +7,13 @@
 
 `timescale 1ps / 1ps
 
+`ifdef BASIL_SBUS
+    `define SPLIT_BUS
+`elsif BASIL_TOPSBUS
+    `define SPLIT_BUS
+`endif
+
+`ifndef BASIL_SBUS
 `include "utils/bus_to_ip.v"
 
 `include "utils/cdc_syncfifo.v"
@@ -15,12 +22,20 @@
 
 `include "bram_fifo/bram_fifo_core.v"
 `include "bram_fifo/bram_fifo.v"
+`else
+    $fatal("Sbus modules not implemented yet");
+`endif
 
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
     input wire  [31:0]  BUS_ADD,
-    inout wire  [31:0]  BUS_DATA,
+`ifndef SPLIT_BUS
+    inout wire  [31:0]   BUS_DATA,
+`else
+    input wire  [31:0]   BUS_DATA_IN,
+    output wire [31:0]   BUS_DATA_OUT,
+`endif
     input wire          BUS_RD,
     input wire          BUS_WR,
     output wire         BUS_BYTE_ACCESS
@@ -35,6 +50,16 @@ localparam FIFO_HIGHADDR_DATA = 32'h9000_0000-1;
 localparam ABUSWIDTH = 32;
 assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
 
+// Connect tb internal bus to external split bus
+`ifdef BASIL_TOPSBUS
+    wire [31:0] BUS_DATA;
+    assign BUS_DATA = BUS_DATA_IN;
+    assign BUS_DATA_OUT = BUS_DATA;
+`elsif BASIL_SBUS
+    wire [31:0] BUS_DATA_OUT_1;
+    assign BUS_DATA_OUT = BUS_DATA_OUT_1;
+`endif
+
 wire FIFO_READ_RX;
 wire FIFO_EMPTY_RX;
 wire [31:0] FIFO_DATA_RX;
@@ -43,19 +68,32 @@ assign cdc_fifo_write = (BUS_ADD >= 32'h1000 && BUS_ADD < 32'h8000) & BUS_WR;
 
 wire fifo_full, cdc_fifo_empty;
 wire [7:0] cdc_data_out;
+
+`ifndef BASIL_SBUS
 cdc_syncfifo #(
+`else
+cdc_syncfifo_sbus #(
+`endif
     .DSIZE(8),
     .ASIZE(3)
 ) cdc_syncfifo_i (
     .rdata(cdc_data_out),
     .wfull(),
     .rempty(cdc_fifo_empty),
+`ifndef BASIL_SBUS
     .wdata(BUS_DATA),
+`else
+    .wdata(BUS_DATA_IN),
+`endif
     .winc(cdc_fifo_write), .wclk(BUS_CLK), .wrst(BUS_RST),
     .rinc(!fifo_full), .rclk(BUS_CLK), .rrst(BUS_RST)
 );
 
+`ifndef BASIL_SBUS
 fifo_8_to_32 #(
+`else
+fifo_8_to_32_sbus #(
+`endif
     .DEPTH(1024)
 ) fifo_8_to_32_i (
     .RST(BUS_RST),
@@ -68,10 +106,14 @@ fifo_8_to_32 #(
     .DATA_OUT(FIFO_DATA)
 );
 
-
 wire FIFO_READ, FIFO_EMPTY;
 wire [31:0] FIFO_DATA;
+
+`ifndef BASIL_SBUS
 bram_fifo #(
+`else
+bram_fifo_sbus #(
+`endif
     .BASEADDR(FIFO_BASEADDR),
     .HIGHADDR(FIFO_HIGHADDR),
     .BASEADDR_DATA(FIFO_BASEADDR_DATA),
@@ -81,7 +123,12 @@ bram_fifo #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -95,9 +142,11 @@ bram_fifo #(
     .FIFO_READ_ERROR()
 );
 
+`ifndef VERILATOR_SIM
 initial begin
     $dumpfile("test_SimFifo8to32.vcd");
     $dumpvars(0);
 end
+`endif
 
 endmodule

tests/test_SimFifo8to32_sbus.py

@@ -0,0 +1,28 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+import unittest
+import sys
+
+from tests.test_SimFifo8to32 import TestSimFifo8to32
+
+
+if __name__ == '__main__':
+    # https://stackoverflow.com/a/2081750
+    test_loader = unittest.TestLoader()
+    test_names = test_loader.getTestCaseNames(TestSimFifo8to32)
+
+    suite = unittest.TestSuite()
+
+# TODO: add sbus versions of used modules
+#    for test_name in test_names:
+#        suite.addTest(TestSimFifo8to32(testname=test_name, tb='test_SimFifo8to32.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='sbus'))
+    for test_name in test_names:
+        suite.addTest(TestSimFifo8to32(testname=test_name, tb='test_SimFifo8to32.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='top'))
+
+    result = unittest.TextTestRunner().run(suite)
+    sys.exit(not result.wasSuccessful())