Merge 7f84d10 into e738190

.github/workflows/regression-tests.yml

@@ -0,0 +1,64 @@
+name: Regression Tests
+
+on: [push, pull_request]
+
+jobs:
+
+  lint-flake8:
+    runs-on: ubuntu-latest
+    name: flake8
+    strategy:
+      fail-fast: false
+      matrix:
+        python-version: [3.8]
+    steps:
+    - uses: actions/checkout@v2
+    - name: Set up Python ${{matrix.python-version}}
+      uses: actions/setup-python@v2
+      with:
+        python-version: ${{matrix.python-version}}
+    - name: flake8
+      run: |
+        pip install flake8
+        flake8
+
+  tests:
+    name: Python ${{matrix.python-version}}
+    runs-on: ubuntu-20.04
+
+    strategy:
+      matrix:
+        python-version: [3.7, 3.8]
+
+    steps:
+    - uses: actions/checkout@v1
+    - uses: conda-incubator/setup-miniconda@v2
+      with:
+        auto-update-conda: true
+        python-version: ${{ matrix.python-version }}
+
+    - name: Install Conda dependencies
+      shell: bash -l {0}
+      run: |
+        conda info -a
+        conda install numpy bitarray nose pyyaml coverage six
+
+    - name: Install Python dependencies
+      shell: bash -l {0}
+      run: |
+        pip install pyvisa pyvisa-sim coveralls cocotb==1.2.0
+  
+    - name: Install Icarus Verilog
+      run: |
+        sudo apt install -y --no-install-recommends iverilog
+
+    - name: Install basil
+      shell: bash -l {0}
+      run: |
+        pip install -e .
+
+    - name: Test
+      shell: bash -l {0}
+      run: |
+        pip install -e .
+        nosetests --with-coverage --cover-package=basil  tests/test_*.py examples/*/*/test_*.py

basil/HL/MIO_PLL.py

@@ -5,10 +5,12 @@
 # ------------------------------------------------------------
 #
 
+# E221 multiple spaces before operator
+# flake8: noqa 
+
 import logging
 
 from basil.HL.HardwareLayer import HardwareLayer
-import six
 
 logger = logging.getLogger(__name__)
 
@@ -53,7 +55,7 @@ class MIO_PLL(HardwareLayer):
     CY22150_LCLK4_EN                 = 0x08
     CY22150_CLK5_EN                  = 0x10
     CY22150_CLK6_EN                  = 0x20
-   # constants
+    # constants
     CY22150_DEF_INPDRV               = 0x28  # input range for 48 MHz reference clock oszillator
     CY22150_DEF_INPCAP               = 0x00  # no load capacitor
     CY22150_FREF_FX                  = 48.0  # reference clock, from USB controller

basil/dut.py

@@ -8,7 +8,6 @@
 from importlib import import_module
 from inspect import getmembers, isclass
 from yaml import safe_load
-import sys
 import warnings
 from collections import OrderedDict
 from six import string_types
@@ -43,7 +42,7 @@ def __init__(self, conf):
 
     def _open_conf(self, conf):
         def isFile(f):
-            return isinstance(f, file) if sys.version_info[0] == 2 else hasattr(f, 'read')
+            return hasattr(f, 'read')
 
         conf_dict = {}
         if not conf:

basil/utils/utils.py

@@ -44,7 +44,10 @@ def bitarray_to_byte_array(bitarr):
     bs = (bs * 0x0202020202 & 0x010884422010) % 1023
     return array('B', bs.astype(np.uint8))
 
+
 # Python 2/3 compatibility function for array.tobytes function
+
+
 try:
     array.tobytes
 except AttributeError:  # Python 2

examples/MIO/tb/test_SimExample.py

@@ -60,5 +60,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

examples/lx9/host/lx9.py

@@ -149,7 +149,7 @@ def _clear_strobes(self):
 
 chip['PIXEL_REG'][:] = bitarray('1111111010001100' * 8)
 print(chip['PIXEL_REG'])
-#chip['PIXEL_REG'][0] = 0
+# chip['PIXEL_REG'][0] = 0
 
 print("program pixel register...")
 chip.program_pixel_reg()

examples/mio3_eth_gpac/mio3_eth_gpac.py

@@ -16,4 +16,3 @@
 chip['CONTROL']['LED'] = 0xa5
 
 chip['CONTROL'].write()
-

examples/mio_pixel/pixel.py

@@ -6,7 +6,6 @@
 #
 
 
-
 import time
 
 import numpy as np

examples/mio_pixel/tests/test_Sim.py

@@ -13,9 +13,8 @@
 from bitarray import bitarray
 
 from basil.utils.sim.utils import cocotb_compile_and_run, cocotb_compile_clean, get_basil_dir
-
 sys.path.append(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
-import pixel
+import pixel # noqa E402
 
 
 class TestPixel(unittest.TestCase):
@@ -86,5 +85,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

examples/mio_sram_test/tests/test_Sim.py

@@ -213,5 +213,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

examples/mmc3_eth/test/test_mmc3_eth.py

@@ -96,11 +96,11 @@ def test(self):
             time.sleep(0.01)
             tick = int(time.time() - start_time)
             if tick != tick_old:
-                print (tick)
+                print(tick)
                 tick_old = tick
 
             if doprint:
-                print (data)
+                print(data)
 
             for i in data:
                 if i < (len(data) - 1):

setup.py

@@ -34,7 +34,7 @@ def package_files(directory):
 setup(
     name='basil_daq',
     version=version,
-    python_requires='>=2.7,!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*',
+    python_requires='>=3.7',
     description='Basil - a data acquisition and system testing framework',
     url='https://github.com/SiLab-Bonn/basil',
     license='BSD 3-Clause ("BSD New" or "BSD Simplified") License',

tests/test_BitLogic.py

@@ -232,13 +232,13 @@ def test_get_slicing_and_indexing(self):
 
     def test_set_slicing_and_indexing(self):
         bl = BitLogic('00000000')
-        bl[3:1] = True #same as 1
+        bl[3:1] = True  # same as 1
         self.assertEqual(bl, bitarray('01000000'))
         bl = BitLogic('00000000')
-        bl[3:1] = 0b111 
+        bl[3:1] = 0b111
         self.assertEqual(bl, bitarray('01110000'))
         bl = BitLogic('11111111')
-        bl[3:1] = False #same as 0
+        bl[3:1] = False  # same as 0
         self.assertEqual(bl, bitarray('10001111'))
         bl = BitLogic('00000000')
         bl[3:1] = 1
@@ -402,5 +402,6 @@ def test_set_item_negative(self):
         bl[-1:-2] = 2
         self.assertEqual(bl, bitarray('01000001'))
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_RegisterHardwareLayer.py

@@ -195,5 +195,6 @@ def test_write_non_existing(self):
     def test_wrong_size(self):
         self.assertRaises(TypeError, self.dut['test_register'].set_value, 131, addr=0, size=7, offset=7)
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_SimAdcRx.py

@@ -132,5 +132,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_SimGpio.py

@@ -26,13 +26,13 @@
     interface : INTF
     base_addr : 0x0000
     size      : 24
-    
+
   - name      : GPIO2
     type      : gpio
     interface : INTF
     base_addr : 0x0010
     size      : 16
-    
+
 registers:
   - name        : GPIO
     type        : StdRegister
@@ -89,5 +89,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_SimI2c.py

@@ -78,5 +78,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_SimJtagGpio.py

@@ -267,5 +267,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_SimSeq.py

@@ -195,5 +195,6 @@ def tearDown(self):
         self.chip.close()  # let it close connection and stop simulator
         cocotb_compile_clean()
 
+
 if __name__ == '__main__':
     unittest.main()

tests/test_SimTdc.py

@@ -162,7 +162,6 @@ def test_broadcasting(self):
             self.assertEqual(data0[0], data1[0])  # Compare TDC0 with TDC1
             self.assertEqual(data0[0], data2[0])  # Compare TDC0 with TDC2
 
-
 #     def test_tdc_delay(self):
 #         pass
 #