Update workflows (#208)

* PRJ: Update workflow (verilog version, python version) --------- Co-authored-by: Yannick Dieter <yannick.manuel.dieter@cern.ch> Co-authored-by: Christian Bespin <11457592+cbespin@users.noreply.github.com> Co-authored-by: Christian Bespin <silab@debian-BULLSEYE-live-builder-AMD64>
SiLab-Bonn · Apr 22, 2024 · ba55498 · ba55498
1 parent 92d4147
commit ba55498
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Showing 7 changed files with 19 additions and 19 deletions.
diff --git a/.github/workflows/regression-tests.yml b/.github/workflows/regression-tests.yml
@@ -16,7 +16,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        python-version: [3.8]
+        python-version: [3.11]
     steps:
     - uses: actions/checkout@v2
     - name: Set up Python ${{matrix.python-version}}
@@ -31,32 +31,32 @@ jobs:
   tests:
 
     name: Python ${{matrix.python-version}} | ${{matrix.sim}} 
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
     env:
       SIM: ${{matrix.sim}}
 
     strategy:
       fail-fast: false
       matrix:
         include:
-
           - sim: icarus
-            python-version: 3.7
+            python-version: '3.11'
 
           - sim: icarus
-            python-version: 3.8
+            python-version: '3.10'
 
           - sim: verilator
-            sim-version: v4.106
-            python-version: 3.8
+            sim-version: v5.020
+            python-version: '3.10'
             pytest-marker: "-m verilator"
 
     steps:
     - uses: actions/checkout@v1
-    - uses: conda-incubator/setup-miniconda@v2
+    - name: Set up Anaconda ${{matrix.python-version}}
+      uses: conda-incubator/setup-miniconda@v2
       with:
         auto-update-conda: true
-        python-version: ${{ matrix.python-version }}
+        python-version: ${{matrix.python-version}}
 
     - name: Install Conda dependencies
       shell: bash -l {0}
@@ -67,12 +67,12 @@ jobs:
     - name: Install Python dependencies
       shell: bash -l {0}
       run: |
-        pip install pyvisa pyvisa-sim pytest coveralls pytest-cov cocotb==1.5.2
+        pip install pyvisa pyvisa-sim pytest coveralls pytest-cov cocotb>=1.8.1 cocotb-bus
   
     - name: Install Verilator
       if: matrix.sim == 'verilator'
       run: |
-        sudo apt install -y --no-install-recommends make g++ perl python3 autoconf flex bison libfl2 libfl-dev zlibc zlib1g zlib1g-dev
+        sudo apt install -y --no-install-recommends make g++ help2man perl autoconf flex bison libfl2 libfl-dev zlib1g zlib1g-dev
         git clone https://github.com/verilator/verilator.git -b ${{matrix.sim-version}}
         cd verilator
         autoconf

diff --git a/basil/HL/JtagMaster.py b/basil/HL/JtagMaster.py
@@ -102,7 +102,7 @@ def scan_ir(self, data, readback=True):
         bit_number = self._test_input(data)
         self.SIZE = bit_number
 
-        if type(data[0]) == BitLogic:
+        if isinstance(data[0], BitLogic):
             data_byte = self._bitlogic2bytes(data)
         else:
             data_byte = self._raw_data2bytes(data)
@@ -135,7 +135,7 @@ def scan_dr(self, data, readback=True, word_size=None):
             self.WORD_COUNT = bit_number // word_size
             self.SIZE = word_size
 
-        if type(data[0]) == BitLogic:
+        if isinstance(data[0], BitLogic):
             data_byte = self._bitlogic2bytes(data)
         else:
             data_byte = self._raw_data2bytes(data)

diff --git a/basil/TL/Socket.py b/basil/TL/Socket.py
@@ -37,7 +37,7 @@ def close(self):
         self._sock.close()
 
     def write(self, data):
-        if type(data) == bytes:
+        if isinstance(data, bytes):
             cmd = data
         else:
             cmd = data.encode(self.encoding)

diff --git a/basil/firmware/modules/utils/CG_MOD_neg.v b/basil/firmware/modules/utils/CG_MOD_neg.v
@@ -18,7 +18,7 @@ input ck_in,enable;
 output ck_out;
 reg enl;
 
-always @(ck_in or enable)
+always_latch
 if (ck_in)
     enl = enable;
 assign ck_out = ck_in | ~enl;

diff --git a/basil/firmware/modules/utils/CG_MOD_pos.v b/basil/firmware/modules/utils/CG_MOD_pos.v
@@ -18,7 +18,7 @@ wire ck_inb;
 reg enl;
 
 assign ck_inb = ~ck_in;
-always @(ck_inb or enable)
+always_latch
 if (ck_inb)
     enl = enable;
 assign ck_out = ck_in & enl;

diff --git a/basil/utils/sim/utils.py b/basil/utils/sim/utils.py
@@ -61,7 +61,7 @@ def cocotb_makefile(sim_files, top_level='tb', test_module='basil.utils.sim.Test
 #export COCOTB=$(shell SPHINX_BUILD=1 python -c "import cocotb; import os; print(os.path.dirname(os.path.dirname(os.path.abspath(cocotb.__file__))))")
 #export PYTHONPATH=$(shell python -c "from distutils import sysconfig; print(sysconfig.get_python_lib())"):$(COCOTB)
 #export LD_LIBRARY_PATH=/lib/x86_64-linux-gnu:$(PYTHONLIBS)
-export PYTHONHOME=$(shell python -c "from distutils.sysconfig import get_config_var; print(get_config_var('prefix'))")
+#export PYTHONHOME=$(shell python -c "from distutils.sysconfig import get_config_var; print(get_config_var('prefix'))")
 
 ifeq ($(SIM),questa)
     EXTRA_ARGS += $(NOT_ICARUS_DEFINES)

diff --git a/tests/test_SimGpio.v b/tests/test_SimGpio.v
@@ -53,12 +53,12 @@ localparam GPIO2_HIGHADDR = 16'h001f;
     assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2;
 `endif
 
-/* verilator lint_off UNOPT */
+/* verilator lint_off UNOPTFLAT */
 wire [23:0] IO;
 
 assign IO[15:8] = IO[7:0];
 assign IO[23:20] = IO[19:16];
-/* verilator lint_on UNOPT */
+/* verilator lint_on UNOPTFLAT */
 
 `ifndef BASIL_SBUS
 gpio #(