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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1 +1 @@ | ||
| 2.4.2 | ||
| 2.4.3 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| # | ||
| # ------------------------------------------------------------ | ||
| # Copyright (c) All rights reserved | ||
| # SiLab, Institute of Physics, University of Bonn | ||
| # ------------------------------------------------------------ | ||
| # | ||
|
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| from basil.HL.RegisterHardwareLayer import HardwareLayer | ||
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| class Arduino(HardwareLayer): | ||
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| '''Implement functions to steer the Arduino digital IO using the BASIL Arduino firmware. | ||
| ''' | ||
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| def __init__(self, intf, conf): | ||
| super(Arduino, self).__init__(intf, conf) | ||
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| def set_output(self, channel, value): | ||
| if value == 'ON': | ||
| value = 1 | ||
| elif value == 'OFF': | ||
| value = 0 | ||
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| if value != 0 and value != 1: | ||
| raise ValueError('The value for the output has to be ON, OFF, 0 or 1') | ||
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| if channel == 'ALL': | ||
| channel = 99 # All channels are internally channel 99 | ||
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| if channel < 2 or (channel > 13 and channel != 99): | ||
| raise ValueError('Arduino supports only 14 IOs and pins 0 and 1 are blocked by Serial communication. %d is out of range' % channel) | ||
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| self._intf.write('GPIO%d %d' % (channel, value)) | ||
| if self._intf.read() == 'r': # Wait for response of Arduino | ||
| raise RuntimeError('Got no or wrong response from Arduino!') |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,126 @@ | ||
| # | ||
| # ------------------------------------------------------------ | ||
| # Copyright (c) All rights reserved | ||
| # SiLab, Institute of Physics, University of Bonn | ||
| # ------------------------------------------------------------ | ||
| # | ||
| import yaml | ||
|
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| from basil.HL.HardwareLayer import HardwareLayer | ||
| from basil.RL.StdRegister import StdRegister | ||
| from basil.utils.BitLogic import BitLogic | ||
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| class JtagGpio(HardwareLayer): | ||
| '''GPIO based JTAG interface | ||
| ''' | ||
| jtag_gpio_yaml = """ | ||
| name : GPIO | ||
| type : StdRegister | ||
| driver : None | ||
| size : 8 | ||
| fields: | ||
| - name : RESETB | ||
| size : 1 | ||
| offset : 0 | ||
| - name : TCK | ||
| size : 1 | ||
| offset : 1 | ||
| - name : TMS | ||
| size : 1 | ||
| offset : 2 | ||
| - name : TDI | ||
| size : 1 | ||
| offset : 3 | ||
| - name : TDO | ||
| size : 1 | ||
| offset : 4 | ||
| """ | ||
|
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| def __init__(self, intf, conf): | ||
| super(JtagGpio, self).__init__(intf, conf) | ||
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| cfg = yaml.load(self.jtag_gpio_yaml) | ||
| self.reg = StdRegister(driver=None, conf=cfg) | ||
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| # self.RESETB = 0 | ||
| # self.TCK = 0 | ||
| # self.reg['TMS'] = 0 | ||
| # self.TDI = 0 | ||
| # self.TD0 = 0 | ||
|
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| def init(self): | ||
| pass | ||
|
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| def reset(self): | ||
| self.reg['RESETB'] = 0 | ||
| self._write(tck=False) | ||
| self.reg['RESETB'] = 1 | ||
| self._write(tck=False) | ||
| self.tms_reset() | ||
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| def tms_reset(self): | ||
| for _ in range(5): | ||
| self.reg['TMS'] = 1 | ||
| self._write() | ||
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| self.reg['TMS'] = 0 | ||
| self._write() # idle | ||
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| def scan_ir(self, data): | ||
| self.reg['TMS'] = 1 | ||
| self._write() | ||
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| self.reg['TMS'] = 1 | ||
| self._write() # select ir | ||
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| return self._scan(data) | ||
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| def scan_dr(self, data): | ||
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| self.reg['TMS'] = 1 | ||
| self._write() # select dr | ||
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| return self._scan(data) | ||
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| def _scan(self, data): | ||
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| self.reg['TMS'] = 0 | ||
| self._write() # capture | ||
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| self.reg['TMS'] = 0 | ||
| ret_bit = self._write() # shift | ||
|
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| ret = [] | ||
| for dev in range(len(data)): | ||
| dev_ret = BitLogic(len(data[dev])) | ||
| for bit in range(len(data[dev])): | ||
| if dev == len(data) - 1 and bit == len(data[dev]) - 1: | ||
| self.reg['TMS'] = 1 # exit1 | ||
| self.reg['TDI'] = data[dev][bit] | ||
| dev_ret[bit] = ret_bit | ||
| ret_bit = self._write() | ||
| ret.append(dev_ret) | ||
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| self.reg['TDI'] = 0 | ||
| self.reg['TMS'] = 1 | ||
| self._write() # update | ||
|
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| self.reg['TMS'] = 0 | ||
| self._write() # idle | ||
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| return ret | ||
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| def _write(self, tck=True): | ||
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| self._intf.set_data(self.reg.tobytes()) | ||
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| if(tck): | ||
| self.reg['TCK'] = 0 | ||
| self._intf.set_data(self.reg.tobytes()) | ||
| self.reg['TCK'] = 1 | ||
| self._intf.set_data(self.reg.tobytes()) | ||
| self.reg['TCK'] = 0 | ||
| self._intf.set_data(self.reg.tobytes()) | ||
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| return (self._intf.get_data()[0] & 0b0010000) >> 4 # TODO: |
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