v2.4.12

• adding high resolution time stamp module
• adding software trigger (TLU/TRIGGER FSM)
• adding reset signal for the timestamp (TLU/TRIGGER FSM)
• increasing trigger delay parameter from 4 bits to 8 bits (TLU/TRIGGER FSM)
• improvements and bug fixing of UDP to BUS (RBCP) interface (SiTCP TL)
• adding TCP to BUS module (as a replacement for RBCP)
• implement close() for SiTCP TL
• adding no_calibration parameter to FEI4QuadModuleAdapterCard
• adding TCP and UDP speed test (firmware and example)
• lots of code cleanup