Design Engineer at Intel. SystemVerilog design and verification in my spare time.
- Austin, TX
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pipelined-mips
pipelined-mips PublicPipelined MIPS processor based on Harris & Harris Digital Design and Computer Architecture, 2nd Ed.
SystemVerilog 2
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goldfinch
goldfinch PublicImage sharpening algorithm behavioral model in Python as well as a SystemC representation
C++
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