Merge 61c2a3f into 19ed402

gfe_integration_tests/test_extra_monitor/sdram_writer.py

@@ -21,44 +21,41 @@
 from spinn_front_end_common.abstract_models.impl import (
     MachineDataSpecableVertex)
 from spinn_front_end_common.utilities.utility_objs import ExecutableType
-from spinn_front_end_common.utilities import constants
 from spinn_front_end_common.interface.simulation import simulation_utilities
-from spinn_front_end_common.utilities.constants import SIMULATION_N_BYTES
+from spinn_front_end_common.utilities.constants import (
+    SIMULATION_N_BYTES, SYSTEM_BYTES_REQUIREMENT)
+
+_SDRAM_READING_SIZE_IN_BYTES_CONVERTER = 1024 * 1024
+_CONFIG_REGION_SIZE = 4
 
 
 class SDRAMWriter(
         MachineVertex, MachineDataSpecableVertex, AbstractHasAssociatedBinary):
-
-    SDRAM_READING_SIZE_IN_BYTES_CONVERTER = 1024*1024
-    CONFIG_REGION_SIZE = 4
-
     DATA_REGIONS = Enum(
         value="DATA_REGIONS",
         names=[('SYSTEM', 0),
                ('CONFIG', 1),
                ('DATA', 2)])
 
-    def __init__(self, mbs):
-        self._mbs = mbs * self.SDRAM_READING_SIZE_IN_BYTES_CONVERTER
+    def __init__(self, mebibytes):
+        self._size = mebibytes * _SDRAM_READING_SIZE_IN_BYTES_CONVERTER
         super(SDRAMWriter, self).__init__(label="speed", constraints=None)
 
     @property
     def mbs_in_bytes(self):
-        return self._mbs
+        return self._size
 
     @property
     def resources_required(self):
         return ResourceContainer(sdram=ConstantSDRAM(
-            self._mbs + constants.SYSTEM_BYTES_REQUIREMENT +
-            self.CONFIG_REGION_SIZE))
+            self._size + SYSTEM_BYTES_REQUIREMENT + _CONFIG_REGION_SIZE))
 
     def get_binary_start_type(self):
         return ExecutableType.USES_SIMULATION_INTERFACE
 
     def generate_machine_data_specification(
             self, spec, placement, machine_graph, routing_info, iptags,
             reverse_iptags, machine_time_step, time_scale_factor):
-
         # Reserve SDRAM space for memory areas:
         self._reserve_memory_regions(spec)
 
@@ -69,22 +66,23 @@ def generate_machine_data_specification(
             time_scale_factor))
 
         spec.switch_write_focus(self.DATA_REGIONS.CONFIG.value)
-        spec.write_value(self._mbs)
+        spec.write_value(self._size)
 
         # End-of-Spec:
         spec.end_specification()
 
     def _reserve_memory_regions(self, spec):
         spec.reserve_memory_region(
-            region=self.DATA_REGIONS.SYSTEM.value, size=SIMULATION_N_BYTES,
+            region=self.DATA_REGIONS.SYSTEM.value,
+            size=SIMULATION_N_BYTES,
             label='systemInfo')
         spec.reserve_memory_region(
             region=self.DATA_REGIONS.CONFIG.value,
-            size=self.CONFIG_REGION_SIZE,
+            size=_CONFIG_REGION_SIZE,
             label="config")
         spec.reserve_memory_region(
             region=self.DATA_REGIONS.DATA.value,
-            size=self._mbs,
+            size=self._size,
             label="data region")
 
     def get_binary_file_name(self):

gfe_integration_tests/test_extra_monitor/test_extra_monitor.py

@@ -22,16 +22,19 @@
 from gfe_integration_tests.test_extra_monitor.sdram_writer import SDRAMWriter
 
 _ONE_WORD = struct.Struct("<I")
+_MONITOR_VERTICES = 'MemoryExtraMonitorVertices'
+_GATHERER_MAP = 'MemoryMCGatherVertexToEthernetConnectedChipMapping'
+_TRANSFER_SIZE_MEGABYTES = 20
 
 
-def get_data_region_address(transceiver, placement):
+def get_data_region_address(transceiver, placement, region):
     # Get the App Data for the core
     app_data_base_address = transceiver.get_cpu_information_from_core(
         placement.x, placement.y, placement.p).user[0]
 
     # Get the provenance region base address
     base_address_offset = get_region_base_address_offset(
-        app_data_base_address, SDRAMWriter.DATA_REGIONS.DATA.value)
+        app_data_base_address, region.value)
     return _ONE_WORD.unpack(transceiver.read_memory(
         placement.x, placement.y, base_address_offset, _ONE_WORD.size))[0]
 
@@ -49,59 +52,58 @@ def check_data(data):
             start_value += 1
 
 
+def _get_monitor_placement(monitor_vertices, placement):
+    """ Get the receiver placement on the same chip as a given placement
+    """
+    for vertex in monitor_vertices:
+        vtx_plt = sim.placements().get_placement_of_vertex(vertex)
+        if vtx_plt.x == placement.x and vtx_plt.y == placement.y:
+            return vtx_plt
+    raise Exception("no extra monitor on same chip as {}".format(placement))
+
+
 def test_extra_monitor():
-    mbs = 20
+    mbs = _TRANSFER_SIZE_MEGABYTES
 
     # setup system
     globals_variables.unset_simulator()
     sim.setup(model_binary_folder=os.path.dirname(__file__),
               n_chips_required=2)
 
     # build verts
-    writer = SDRAMWriter(mbs)
+    writer_vertex = SDRAMWriter(mbs)
 
     # add verts to graph
-    sim.add_machine_vertex_instance(writer)
-
+    sim.add_machine_vertex_instance(writer_vertex)
     sim.run(12)
 
-    # get placements for extraction
-    placements = sim.placements()
-    machine = sim.machine()
-
-    writer_placement = placements.get_placement_of_vertex(writer)
-    writer_chip = machine.get_chip_at(writer_placement.x, writer_placement.y)
-    writer_nearest_ethernet = machine.get_chip_at(
-        writer_chip.nearest_ethernet_x, writer_chip.nearest_ethernet_y)
-
-    extra_monitor_vertices = sim.globals_variables.\
-        get_simulator()._last_run_outputs['MemoryExtraMonitorVertices']
-    extra_monitor_gatherers = sim.globals_variables.\
-        get_simulator()._last_run_outputs[
-            'MemoryMCGatherVertexToEthernetConnectedChipMapping']
+    writer_placement = sim.placements().get_placement_of_vertex(writer_vertex)
+    writer_chip = sim.machine().get_chip_at(
+        writer_placement.x, writer_placement.y)
 
-    receiver = None
-    gatherer = extra_monitor_gatherers[(writer_nearest_ethernet.x,
-                                        writer_nearest_ethernet.y)]
+    # pylint: disable=protected-access
+    outputs = sim.globals_variables.get_simulator()._last_run_outputs
+    monitor_vertices = outputs[_MONITOR_VERTICES]
+    gatherers = outputs[_GATHERER_MAP]
 
-    for vertex in extra_monitor_vertices:
-        plt = placements.get_placement_of_vertex(vertex)
-        if (plt.x == writer_placement.x and plt.y == writer_placement.y):
-            receiver = vertex
+    receiver_plt = _get_monitor_placement(monitor_vertices, writer_placement)
+    gatherer = gatherers[
+        writer_chip.nearest_ethernet_x, writer_chip.nearest_ethernet_y]
 
     start = float(time.time())
 
     with gatherer.streaming(
-            extra_monitor_gatherers.values(), sim.transceiver(),
-            extra_monitor_vertices, placements):
+            gatherers.values(), sim.transceiver(), monitor_vertices,
+            sim.placements()):
         data = gatherer.get_data(
-            placements.get_placement_of_vertex(receiver),
-            get_data_region_address(sim.transceiver(), writer_placement),
-            writer.mbs_in_bytes, fixed_routes=None)
+            receiver_plt, get_data_region_address(
+                sim.transceiver(), writer_placement,
+                SDRAMWriter.DATA_REGIONS.DATA),
+            writer_vertex.mbs_in_bytes, fixed_routes=None)
 
     end = float(time.time())
 
-    print("time taken to extract {} MB is {}. MBS of {}".format(
+    print("time taken to extract {} MB is {}. Transfer rate: {} Mb/s".format(
         mbs, end - start, (mbs * 8) / (end - start)))
 
     check_data(data)