Add BlackBox.spinalSimWhiteBox

SpinalHDL · Mar 22, 2021 · 225bc80 · 225bc80
1 parent 1c7de63
commit 225bc80
Show file tree

Hide file tree

Showing 2 changed files with 12 additions and 2 deletions.
diff --git a/core/src/main/scala/spinal/core/BlackBox.scala b/core/src/main/scala/spinal/core/BlackBox.scala
@@ -77,6 +77,7 @@ abstract class BlackBox extends Component{
   val librariesUsages = mutable.HashSet[String]();
 
   private var isBb = false
+  var isSpinalSimWb = false
   setBlackBox()
 
   def isBlackBox = isBb
@@ -88,6 +89,10 @@ abstract class BlackBox extends Component{
     isBb = false
   }
 
+  def spinalSimWhiteBox() = {
+    isSpinalSimWb = true
+  }
+
   def addGeneric(name : String, that : Any) : Unit = that match {
     case bt: BaseType => genericElements += Tuple2(name, bt.addTag(GenericValue(bt.head.source)))
     case s: String    => genericElements += Tuple2(name, s)

diff --git a/core/src/main/scala/spinal/core/sim/SimBootstraps.scala b/core/src/main/scala/spinal/core/sim/SimBootstraps.scala
@@ -24,7 +24,7 @@ import java.io.File
 
 import org.apache.commons.io.FileUtils
 import spinal.core.internals.{BaseNode, DeclarationStatement, GraphUtils, PhaseCheck, PhaseContext, PhaseNetlist}
-import spinal.core.{BaseType, Bits, Bool, Component, GlobalData, InComponent, Mem, MemSymbolesMapping, MemSymbolesTag, SInt, SpinalConfig, SpinalEnumCraft, SpinalReport, SpinalTag, SpinalTagReady, UInt, Verilator}
+import spinal.core.{BaseType, Bits, BlackBox, Bool, Component, GlobalData, InComponent, Mem, MemSymbolesMapping, MemSymbolesTag, SInt, SpinalConfig, SpinalEnumCraft, SpinalReport, SpinalTag, SpinalTagReady, UInt, Verilator}
 import spinal.sim._
 
 import scala.collection.mutable
@@ -581,7 +581,12 @@ case class SpinalSimConfig(
     val uniqueId = SimWorkspace.allocateUniqueId()
     new File(s"tmp").mkdirs()
     new File(s"tmp/job_$uniqueId").mkdirs()
-    val config = _spinalConfig.copy(targetDirectory = s"tmp/job_$uniqueId")
+    val config = _spinalConfig.copy(targetDirectory = s"tmp/job_$uniqueId").addTransformationPhase(new PhaseNetlist {
+      override def impl(pc: PhaseContext): Unit = pc.walkComponents{
+        case b : BlackBox if b.isBlackBox && b.isSpinalSimWb => b.clearBlackBox()
+        case _ =>
+      }
+    })
     val report = _backend match {
       case SpinalSimBackendSel.VERILATOR => {
         config.addTransformationPhase(new SwapTagPhase(SimPublic, Verilator.public))