Axi4 add AW allStrb feature

SpinalHDL · Apr 24, 2023 · 239aa6d · 239aa6d
1 parent 8acff23
commit 239aa6d
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Showing 4 changed files with 15 additions and 8 deletions.
diff --git a/lib/src/main/scala/spinal/lib/bus/amba4/axi/Axi4.scala b/lib/src/main/scala/spinal/lib/bus/amba4/axi/Axi4.scala
@@ -49,6 +49,7 @@ case class Axi4Config(addressWidth : Int,
                       useResp      : Boolean = true,
                       useProt      : Boolean = true,
                       useStrb      : Boolean = true,
+                      useAllStrb   : Boolean = false,
                       arUserWidth  : Int = -1,
                       awUserWidth  : Int = -1,
                       rUserWidth   : Int = -1,

diff --git a/lib/src/main/scala/spinal/lib/bus/amba4/axi/Axi4Channel.scala b/lib/src/main/scala/spinal/lib/bus/amba4/axi/Axi4Channel.scala
@@ -9,7 +9,7 @@ import spinal.lib._
  * Definition of the Write/Read address channel
  * @param config Axi4 configuration class
  */
-class Axi4Ax(val config: Axi4Config,val userWidth : Int) extends Bundle {
+class Axi4Ax(val config: Axi4Config,val userWidth : Int, readOnly : Boolean) extends Bundle {
   val addr   = UInt(config.addressWidth bits)
   val id     = if(config.useId)     UInt(config.idWidth bits)   else null
   val region = if(config.useRegion) Bits(4 bits)                else null
@@ -21,6 +21,7 @@ class Axi4Ax(val config: Axi4Config,val userWidth : Int) extends Bundle {
   val qos    = if(config.useQos)    Bits(4 bits)                else null
   val user   = if(userWidth >= 0)   Bits(userWidth bits)        else null
   val prot   = if(config.useProt)   Bits(3 bits)                else null
+  val allStrb = if(config.useAllStrb && !readOnly) Bool()       else null
 
   import Axi4.burst._
 
@@ -38,7 +39,7 @@ class Axi4Ax(val config: Axi4Config,val userWidth : Int) extends Bundle {
   def setQos(qosType : Bits) : Unit = if (config.useQos) qos := qosType
   def setProt(protType : Bits) : Unit = if (config.useProt) prot := protType
 
-  override def clone: this.type = new Axi4Ax(config,userWidth).asInstanceOf[this.type]
+  override def clone: this.type = new Axi4Ax(config,userWidth, readOnly).asInstanceOf[this.type]
 
 
   def formalContext() = new Composite(this, "formal") {
@@ -142,13 +143,13 @@ class Axi4Ax(val config: Axi4Config,val userWidth : Int) extends Bundle {
 }
 
 
-class Axi4Aw(config: Axi4Config) extends Axi4Ax(config, config.awUserWidth){
+class Axi4Aw(config: Axi4Config) extends Axi4Ax(config, config.awUserWidth, readOnly = false){
   override def clone: this.type = new Axi4Aw(config).asInstanceOf[this.type]
 }
-class Axi4Ar(config: Axi4Config) extends Axi4Ax(config, config.arUserWidth){
+class Axi4Ar(config: Axi4Config) extends Axi4Ax(config, config.arUserWidth, readOnly = true){
   override def clone: this.type = new Axi4Ar(config).asInstanceOf[this.type]
 }
-class Axi4Arw(config: Axi4Config) extends Axi4Ax(config, config.arwUserWidth){
+class Axi4Arw(config: Axi4Config) extends Axi4Ax(config, config.arwUserWidth, readOnly = false){
   val write = Bool()
   override def clone: this.type = new Axi4Arw(config).asInstanceOf[this.type]
 }
@@ -369,6 +370,7 @@ object Axi4Priv{
     driveWeak(stream,sink,stream.qos,sink.qos,() => B"0000",false,true)
     driveWeak(stream,sink,stream.user,sink.user,() => B(sink.user.range -> false),true,true)
     driveWeak(stream,sink,stream.prot,sink.prot,() => B"010",false,true)
+    driveWeak(stream,sink,stream.allStrb,sink.allStrb,() => False,false,true)
   }
 
 }

diff --git a/lib/src/main/scala/spinal/lib/bus/amba4/axi/Misc.scala b/lib/src/main/scala/spinal/lib/bus/amba4/axi/Misc.scala
@@ -10,8 +10,10 @@ import spinal.lib.bus.bsb.{Bsb, BsbTransaction}
 object Axi4ToAxi4Shared{
   def apply(axi : Axi4): Axi4Shared ={
     val axiShared = new Axi4Shared(axi.config)
-    val arbiter = StreamArbiterFactory().roundRobin.build(new Axi4Ax(axi.config, axi.config.arwUserWidth),2)
-    arbiter.io.inputs(0) << axi.ar.asInstanceOf[Stream[Axi4Ax]]
+    val arbiter = StreamArbiterFactory().roundRobin.build(new Axi4Ax(axi.config, axi.config.arwUserWidth, readOnly = false),2)
+    arbiter.io.inputs(0).arbitrationFrom(axi.ar.asInstanceOf[Stream[Axi4Ax]])
+    arbiter.io.inputs(0).payload.assignSomeByName(axi.ar.asInstanceOf[Stream[Axi4Ax]].payload)
+    if(axi.config.useAllStrb) arbiter.io.inputs(0).allStrb := False
     arbiter.io.inputs(1) << axi.aw.asInstanceOf[Stream[Axi4Ax]]
 
     axiShared.arw.arbitrationFrom(arbiter.io.output)

diff --git a/tester/src/test/scala/spinal/tester/scalatest/Axi4AdapterTester.scala b/tester/src/test/scala/spinal/tester/scalatest/Axi4AdapterTester.scala
@@ -42,6 +42,7 @@ class Axi4UpsizerTester extends SpinalAnyFunSuite {
     val inputMonitor = new Axi4WriteOnlyMonitor(dut.io.input, dut.clockDomain) {
       override def onWriteByte(address: BigInt, data: Byte, id: Int): Unit = {
         //          println(s"I $address -> $data")
+        assert(!writes.contains(address))
         writes(address) = data
       }
     }
@@ -85,7 +86,8 @@ class Axi4UpsizerTester extends SpinalAnyFunSuite {
     val inputAgent = new Axi4ReadOnlyMasterAgent(dut.io.input, dut.clockDomain) {
       override def genAddress(): BigInt = Random.nextInt(1 << 19)
       override def bursts: List[Int] = List(1)
-      override val pageAlignBits = 16
+      override val pageAlignBits = 20
+//      override def lens   =  (0xf0 to 0xff).toList
       override def mappingAllocate(mapping: SizeMapping): Boolean = {
         if(regions.exists(_.overlap(mapping))) return false
         regions += mapping