Merge pull request #1434 from jijingg/reg

[regif] #1409 review close

lib/src/main/scala/spinal/lib/bus/localbus/MemBus.scala

@@ -12,9 +12,12 @@ case class MemBus(c: MemBusConfig) extends Interface with IMasterSlave {
   val wdat  = Bits(c.dw bit)
   val rdat  = Bits(c.dw bit)
 
-  tieGeneric(addr, addGeneric("AW", c.aw))
-  tieGeneric(wdat, addGeneric("DW", c.dw))
-  tieGeneric(rdat, addGeneric("DW", c.dw))
+  addGeneric("AW", c.aw)
+  addGeneric("DW", c.dw)
+
+  tieGeneric(addr, "AW")
+  tieGeneric(wdat, "DW")
+  tieGeneric(rdat, "DW")
 
   override def asMaster(): Unit = {
     out(ce, wr, addr, wdat)

lib/src/main/scala/spinal/lib/bus/localbus/sim/MemBusDriver.scala

@@ -22,7 +22,7 @@ case class MemBusDriver(bus : MemBus, clockdomain : ClockDomain) {
     bus.ce #= true
     bus.wr #= false
     bus.addr #= address
-    bus.wdat #= 1234 //.randomize()
+    bus.wdat.randomize()
     clockdomain.waitSampling()
     bus.ce #= false
     bus.wr.randomize()

lib/src/main/scala/spinal/lib/bus/regif/Block/FifoInst.scala

@@ -9,8 +9,6 @@ abstract class FifoInst(name: String, addr: BigInt, doc: String, grp: GrpTag = n
   val hitDoRead: Bool
   val hitDoWrite : Bool
 
-  val bus = Stream(Bits(bi.busDataWidth bit))
-
   def field(bit: Int, doc: String = "")(name: String) = {
     val section: Range = fieldPtr + bit -1 downto fieldPtr
     fields   += Field(name, Bits(bit bits), section, AccessType.WO, 0, Rerror, doc)

lib/src/main/scala/spinal/lib/bus/regif/Block/RdFifoInst.scala

@@ -6,6 +6,8 @@ import spinal.lib.Stream
 class RdFifoInst(name: String, addr: BigInt, doc: String, grp: GrpTag = null)(bi: BusIf) extends FifoInst(name, addr, doc, grp)(bi){
   override val regType: String = "rFIFO"
 
+  val bus = Stream(Bits(bi.busDataWidth bit))
+
   val hitDoRead = bi.writeAddress === U(addr) && bi.doRead
   val hitDoWrite: Bool = False
   hitDoRead.setName(f"read_hit_0x${addr}%04x", weak = true)

lib/src/main/scala/spinal/lib/bus/regif/Block/WrFifoInst.scala

@@ -1,7 +1,7 @@
 package spinal.lib.bus.regif
 
 import spinal.core._
-import spinal.lib.Stream
+import spinal.lib.{Flow, Stream}
 
 class WrFifoInst(name: String, addr: BigInt, doc: String, grp: GrpTag = null)(bi: BusIf) extends FifoInst(name, addr, doc, grp)(bi){
   override val regType: String = "wFIFO"
@@ -10,6 +10,8 @@ class WrFifoInst(name: String, addr: BigInt, doc: String, grp: GrpTag = null)(bi
   val hitDoWrite = bi.writeAddress === U(addr) && bi.doWrite
   hitDoWrite.setName(f"write_hit_0x${addr}%04x", weak = true)
 
+  val bus = Flow(Bits(bi.busDataWidth bit))
+
   bus.setName(s"${name}_wrfifo")
 
   bus.valid   := hitDoWrite

lib/src/main/scala/spinal/lib/bus/regif/BusIf.scala

@@ -137,93 +137,96 @@ trait BusIf extends BusIfBase {
 
   def newRegAt(address: BigInt, doc: String, grp: GrpTag = null)(implicit symbol: SymbolName) = {
     assert(address % wordAddressInc == 0, s"located Position not align by wordAddressInc: ${wordAddressInc}")
-    val reg = creatReg(symbol.name, address, doc, grp)
+    val reg = createReg(symbol.name, address, doc, grp)
     regPtr = address + wordAddressInc
     reg
   }
 
   def newReg(doc: String, grp: GrpTag = null)(implicit symbol: SymbolName) = {
-    val res = creatReg(symbol.name.toLowerCase(), regPtr, doc, grp)
+    val res = createReg(symbol.name.toLowerCase(), regPtr, doc, grp)
     regPtr += wordAddressInc
     res
   }
 
-  def creatReg(name: String, addr: BigInt, doc: String, grp: GrpTag = null) = {
+  @deprecated("type error fix", "2024.06.03")
+  def creatReg(name: String, addr: BigInt, doc: String, grp: GrpTag = null) = createReg(name, addr, doc, grp)
+
+  def createReg(name: String, addr: BigInt, doc: String, grp: GrpTag = null) = {
     val ret = new RegInst(name, addr, doc, this, grp)
     SliceInsts += ret
     attachAddr(regPtr)
     ret
   }
 
   def newRAM(size: BigInt, doc: String, grp: GrpTag = null)(implicit symbol: SymbolName) = {
-    val res = creatRAM(symbol.name.toLowerCase(), regPtr, size, doc, grp)
+    val res = createRAM(symbol.name.toLowerCase(), regPtr, size, doc, grp)
     regPtr += scala.math.ceil(size.toDouble/wordAddressInc).toLong * wordAddressInc
     res
   }
 
   def newRAMAt(address: BigInt, size: BigInt, doc: String, grp: GrpTag = null)(implicit symbol: SymbolName) = {
     assert(address % wordAddressInc == 0, s"located Position not align by wordAddressInc: ${wordAddressInc}")
-    val res = creatRAM(symbol.name, address, size, doc, grp)
+    val res = createRAM(symbol.name, address, size, doc, grp)
     regPtr = address + scala.math.ceil(size.toDouble/wordAddressInc).toLong * wordAddressInc
     res
   }
 
-  def creatRAM(name: String, addr: BigInt, size: BigInt, doc: String, grp: GrpTag = null) = {
+  def createRAM(name: String, addr: BigInt, size: BigInt, doc: String, grp: GrpTag = null) = {
     val ret = new RamInst(name, addr, size, doc, grp)(this)
     SliceInsts += ret
     attachAddr(SizeMapping(addr, size))
     ret
   }
 
   def newWrFifo(doc: String, grp: GrpTag = null)(implicit symbol: SymbolName): WrFifoInst = {
-    val res = creatWrFifo(symbol.name.toLowerCase(), regPtr, doc, grp)
+    val res = createWrFifo(symbol.name.toLowerCase(), regPtr, doc, grp)
     regPtr += wordAddressInc
     res
   }
 
   def newWrFifoAt(address: BigInt, doc: String, grp: GrpTag = null)(implicit symbol: SymbolName) = {
     assert(address % wordAddressInc == 0, s"located Position not align by wordAddressInc: ${wordAddressInc}")
-    val res = creatWrFifo(symbol.name.toLowerCase(), address, doc, grp)
+    val res = createWrFifo(symbol.name.toLowerCase(), address, doc, grp)
     regPtr = address + wordAddressInc
     res
   }
 
-  def creatWrFifo(name: String, addr: BigInt, Doc: String, grp: GrpTag = null) = {
+  def createWrFifo(name: String, addr: BigInt, Doc: String, grp: GrpTag = null) = {
     val ret = new WrFifoInst(name, addr, Doc, grp)( this)
     SliceInsts += ret
     attachAddr(addr)
     ret
   }
 
-  def creatRdFifo(name: String, addr: BigInt, Doc: String, grp: GrpTag = null): RdFifoInst = {
+  def createRdFifo(name: String, addr: BigInt, Doc: String, grp: GrpTag = null): RdFifoInst = {
     val ret = new RdFifoInst(name, addr, Doc, grp)(this)
     SliceInsts += ret
     attachAddr(addr)
     ret
   }
 
   def newRdFifo(doc: String, grp: GrpTag = null)(implicit symbol: SymbolName): RdFifoInst = {
-    val res = creatRdFifo(symbol.name.toLowerCase(), regPtr, doc, grp)
+    val res = createRdFifo(symbol.name.toLowerCase(), regPtr, doc, grp)
     regPtr += wordAddressInc
     res
   }
 
   def newRdFifoAt(address: BigInt, doc: String, grp: GrpTag = null)(implicit symbol: SymbolName): RdFifoInst = {
     assert(address % wordAddressInc == 0, s"located Position not align by wordAddressInc: ${wordAddressInc}")
-    val res = creatRdFifo(symbol.name.toLowerCase(), address, doc, grp)
+    val res = createRdFifo(symbol.name.toLowerCase(), address, doc, grp)
     regPtr = address + wordAddressInc
     res
   }
 
   def newGrp(maxSize: BigInt, doc: String)(implicit  symbol: SymbolName) = {
-    creatGrp(symbol.name, regPtr, maxSize, doc)
+    createGrp(symbol.name, regPtr, maxSize, doc)
   }
 
   def newGrpAt(address: BigInt, maxSize: BigInt, doc: String)(implicit  symbol: SymbolName) = {
-    creatGrp(symbol.name, address, maxSize, doc)
+    createGrp(symbol.name, address, maxSize, doc)
   }
 
-  def creatGrp(name: String, addr: BigInt, maxSize: BigInt, doc: String) = {
+  def createGrp(name: String, addr: BigInt, maxSize: BigInt, doc: String) = {
     val grp = this.newGrpTag(name)
     val ret = RegSliceGrp(addr, maxSize, doc, grp)(this)
     ret

lib/src/main/scala/spinal/lib/bus/regif/BusIfBase.scala

@@ -23,6 +23,11 @@ trait BusIfBase extends Area{
   val reg_rderr: Bool
   val reg_rdata: Bits
 
+  @deprecated("readData rename to bus_rdata", "2024.12.30")
+  lazy val readData: Bits = bus_rdata
+  @deprecated("readError rename to bus_rderr", "2024.12.30")
+  lazy val readError: Bool = bus_rderr
+
   val writeData: Bits
   val readSync: Boolean = true
   val withStrb: Boolean

lib/src/main/scala/spinal/lib/bus/regif/Factory/IntrBase.scala

@@ -35,7 +35,7 @@ trait IntrBase {
     (signal, raw, mask, status) match {
       case (sig: Bool, raww: Bool, msk: Bool, stt: Bool) => {
         raww.setWhen(sig)
-        stt := sig & (~msk)
+        stt := raww & (~msk)
       }
       case (sig: Bits, raww: Bits, msk: Bits, stt: Bits) => {
         val size = sig.getBitsWidth

tester/src/test/scala/spinal/lib/bus/regif/RegIfMemFifoTester.scala

@@ -12,7 +12,7 @@ class RegifFifoMem extends Component{
   val io = new Bundle{
     val bus = slave(MemBus(MemBusConfig(32, 32)))
     val ram = master(MemBus(MemBusConfig(aw = 8, dw = 32)))
-    val fifowr = master(Stream(Bits(32 bit)))
+    val fifowr = master(Flow(Bits(32 bit)))
     val fiford = slave(Stream(Bits(32 bit)))
   }
 
@@ -45,7 +45,6 @@ class RegIfMemFIfoTB extends RegifFifoMem{
     busdv.simClear()
     io.fiford.valid #= false
     io.fiford.payload #= 0
-    io.fifowr.ready   #= false
     SpinalProgress("simulation start")
     sleep(20)
     this.clockDomain.waitSampling(10)
@@ -92,11 +91,10 @@ class RegIfMemFIfoTB extends RegifFifoMem{
   def testWrFifo() = {
     val datas = (0 to 100).map(i => 0x123400 + i).toList
     val cache = scala.collection.mutable.Queue[Int](datas: _*)
-    io.fifowr.ready #= true
     fork {
       while (true) {
         clockDomain.waitSampling()
-        if (io.fifowr.valid.toBoolean && io.fifowr.ready.toBoolean) {
+        if (io.fifowr.valid.toBoolean) {
           val a = cache.dequeue()
           val b = io.fifowr.payload.toLong
           assert(a == b, s"WrFifo: 0x${a.hexString} != 0x${b.hexString}")