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lib/src/main/scala/spinal/lib/com/uart/TilelinkUartCtrl.scala
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package spinal.lib.com.uart | ||
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import spinal.core._ | ||
import spinal.core.fiber._ | ||
import spinal.lib._ | ||
import spinal.lib.bus.tilelink._ | ||
import spinal.lib.misc.InterruptNode | ||
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object TilelinkUartCtrl{ | ||
def getTilelinkSupport(proposed: bus.tilelink.M2sSupport) = bus.tilelink.SlaveFactory.getSupported( | ||
addressWidth = addressWidth, | ||
dataWidth = 32, | ||
allowBurst = true, | ||
proposed | ||
) | ||
def addressWidth = 6 | ||
} | ||
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case class TilelinkUartCtrl(config : UartCtrlMemoryMappedConfig, tilelinkParameter: BusParameter) extends Component{ | ||
val io = new Bundle{ | ||
val bus = slave(Bus(tilelinkParameter)) | ||
val uart = master(Uart(ctsGen = config.uartCtrlConfig.ctsGen, rtsGen = config.uartCtrlConfig.rtsGen)) | ||
val interrupt = out Bool() | ||
} | ||
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val uartCtrl = new UartCtrl(config.uartCtrlConfig) | ||
io.uart <> uartCtrl.io.uart | ||
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val busCtrl = new SlaveFactory(io.bus, false) | ||
val bridge = uartCtrl.driveFrom32(busCtrl,config) | ||
io.interrupt := bridge.interruptCtrl.interrupt | ||
} | ||
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case class TilelinkUartFiber() extends Area{ | ||
val node = bus.tilelink.fabric.Node.slave() | ||
val interrupt = InterruptNode.master() | ||
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var config = UartCtrlMemoryMappedConfig( | ||
uartCtrlConfig = UartCtrlGenerics(), | ||
initConfig = UartCtrlInitConfig( | ||
baudrate = 115200, | ||
dataLength = 7, // 8 bits | ||
parity = UartParityType.NONE, | ||
stop = UartStopType.ONE | ||
) | ||
) | ||
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val logic = Fiber build new Area{ | ||
node.m2s.supported.load(TilelinkUartCtrl.getTilelinkSupport(node.m2s.proposed)) | ||
node.s2m.none() | ||
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val core = TilelinkUartCtrl(config, node.bus.p) | ||
core.io.bus <> node.bus | ||
interrupt.flag := core.io.interrupt | ||
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val uart = core.io.uart.toIo() | ||
} | ||
} |
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