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Is there any way to add delay at assignment? #1296
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Hi, But overall, i guess it could be added natively. |
Thanks, waiting for offical support. |
Hmm that may take some time, i'm realy underwater. |
Adding delay "# 1" to the code is not a good idea, and some teams even explicitly prohibit it in their specifications . |
Do you need the delay in your testbench? If yes and if you use SpinalSim then you can there is I'm not sure I think its a good idea to add this to the generation capabilities of the core language as its not synthesizable. |
Hi
Is there any way to add delay at assignment? In verilog, I can add delay like below. How can I do it in Spinal?
for combinatorial logic:
for register
I need it in my simulation job. For example, I need to adjust input and output signal latency.
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