Generate diagrams based on SpinalHDL code #1079

ZhaokunHu · 2023-04-08T10:43:54Z

Context, Motivation & Description

This pull request attempts to implement the idea #635 to automatically generate diagrams based on SpinalHDL code. I have created a new function called GenerateDiagrams that can be used in the following way:

HDElkDiagramGen(SpinalVerilog(new _))

This function will generate a new file named _.html .
If you have an internet connection, you can simply open the HTML file and the dependencies will be loaded automatically from the specified URLs. You can see several diagrams in the pages.
These diagrams are generated by the HDElk tool.(https://github.com/davidthings/hdelk ).
If you do not have an internet connection, you need to download the JS packages from this library and place them in the same folder as your HTML file. Then, according to the readme of this library, you need to add the dependencies to your HTML file. Then you can open the HTML file to see the diagrams.

Example:

import spinal.core._
import spinal.lib._

case class FilterConfig(iqWidth: Int,
                        tapNumbers: Int = 33,
                        hwFreq: HertzNumber = 200 MHz,
                        sampleFreq: HertzNumber = 1.92 MHz)

class Filter(fc: FilterConfig) extends Component{
  val din   = slave Flow(Bits(32 bits))
  val dout  = master Flow(Bits(32 bits))
  val flush = in Bool()

  val clockSMP = ClockDomain.external("smp")
  val clockHW = ClockDomain.external("hw")

  val u_fifo_in = StreamFifoCC(
    dataType = Bits(32 bits),
    depth = 8,
    pushClock = clockSMP,
    popClock = clockDomain
  )

  u_fifo_in.io.push << din.toStream
  dout << u_fifo_in.io.pop.toFlow

}

object Filter {
  def main(args: Array[String]): Unit = {
    val fc = FilterConfig(8)
    HDElkDiagramGen(SpinalVerilog(new Filter(fc)))
  }
}

It will generate this diagram:

I have also tested the GenerateDiagrams class on some more complex SpinalHDL projects to ensure the accuracy of the generated diagrams.

One issue that currently exists is that if you use many complex logic operations in your project, the system will automatically generate many registers to implement these operations, and the generated diagrams may become messy as a result.I have tried various methods to simplify the generated diagrams, but the results have been less than satisfactory.Please let me know if you have any thoughts or suggestions on this approach.

Impact on code generation

None

Checklist

Unit tests were added
API changes are or will be documented:
- using Scaladoc comments: /** */?
- on RTD?
- thanks to a new tracking issue on RTD?

Readon · 2023-04-08T13:50:25Z

Good work, Zhaokun.
However, there are still some points could be improved.

Would it better to put the file into directory "lib/src/main/scala/spinal/lib/eda/", which represent it is a tool for eda like funciton.
About the file name GenerateDiagram is really a board topic, how about HDElkDiagramGen or something more specifical, so that diagram generator using other tech could be named properly.
there are still lint errors reported which have been give out at file list. You can run the check locally on your machine first. :)
The function dealAllSignals is really too huge to review and understand. Simplify it would help to improve the quality of code.
On the other hand, the function name dealAllSignals is really vague and it would be better to have a specific name.
It would be nice if you could provide some examples of how to use it as a simulation in the tester subpackage.

kleinai · 2023-04-08T14:24:04Z

This is impressive!

I agree this should be under lib/eda or lib/tools which is where ModuleAnalyzer is.

dealAllSignals could be several smaller functions to make understanding the flow better. It looks like a candidate for abstracting so that other diagram backends could use it. Not that it has to happen in this PR.

Small suggestion, if the design has a fixed frequency maybe we could put that on the diagram too?

Readon · 2023-04-08T14:48:46Z

This is impressive!

I agree this should be under lib/eda or lib/tools which is where ModuleAnalyzer is.

dealAllSignals could be several smaller functions to make understanding the flow better. It looks like a candidate for abstracting so that other diagram backends could use it. Not that it has to happen in this PR.

Small suggestion, if the design has a fixed frequency maybe we could put that on the diagram too?

lib/tools would be better.

Readon · 2023-04-08T14:52:54Z

One more thing, as we talked before, I think the clk is not necessarily connect visibly. There is already clockdomain color, though.

andreasWallner

This looks quite promising, I added a few small comments below that I stumbled over when trying it out/skimming over it.

Apart from that:
I played around a bit, and e.g. this code:

case class Inner() extends Component {
  val io = new Bundle {
    val i = in port Bool()
    val o = out port Bool()
  }
  io.o := RegNext(io.i)
}

will generate this image:

with the output of the register not being connected.

Also this:

case class DiagramDemo() extends Component {
  val io = new Bundle {
    val i = in port Bool()
    val i2 = in port Bool()
    val sel = in port Bool()
    val o = out port Bool()

    val i2b = in port Bits(2 bit)
    val muxout = out port Bool()

    val regout = out port Bool()
  }
  io.muxout := io.i2b.mux(
    0 -> (io.i & io.i2),
    1 -> (io.i | io.i2),
    2 -> (io.i ^ io.i2),
    3 -> (io.i)
  )
  io.regout := RegNextWhen(io.i, io.sel)
  io.o := False
  when(io.i) { io.o := True }
}

generates

Where we see a similar thing with the outputs not being connected, and the assignments to io.o missing completely.

Nitpick: The blue on blue colorscheme of the examples above is kind of hard to read if you ask me.

PS: please also run scalafmt on the code.

lib/src/main/scala/spinal/lib/sim/GenerateDiagram.scala

andreasWallner · 2023-04-08T23:02:14Z

lib/src/main/scala/spinal/lib/sim/GenerateDiagram.scala

+         |<html>
+         |<head>
+         |    <meta charset="UTF-8">
+         |    <title>RTL连接图</title>


Please keep with the remainder of SpinalHDL and use an English title

Sorrry,i forgot to change it.I have changed it to "RTL diagrams based on SpinalHDL code"

That's better, we could also use the component name of the top component in the title e.g. f"{rtl.toplevelName} RTL diagrams"

lib/src/main/scala/spinal/lib/sim/GenerateDiagram.scala

andreasWallner · 2023-04-08T23:04:33Z

lib/src/main/scala/spinal/lib/sim/GenerateDiagram.scala

+    val fileName = rtl.toplevelName + ".html"
+    val file = new File(fileName)
+    val pw = new FileWriter(file)
+    val builder = new StringBuilder()


You have a writer already, why not use that directly (and also pass it to the sub-components for use there?) There is no need to build the string fully in memory?

I changed it based on your advice.

I think I explained poorly: What I meant was to use the writer directly, without the StringBuilder. The StringBuilder will piece everything together in RAM, whereas if you use the writer it can be flushed to disk. But you'd have to pass the writer to GenerateOneDiagram.beginDraw(writer) to do that.
(and if you want/need the output in a String you can still use StringWriter if you use the base Writer as the parameter type)

ZhaokunHu · 2023-04-09T01:24:59Z

This looks quite promising, I added a few small comments below that I stumbled over when trying it out/skimming over it.

Apart from that: I played around a bit, and e.g. this code:
case class Inner() extends Component {
  val io = new Bundle {
    val i = in port Bool()
    val o = out port Bool()
  }
  io.o := RegNext(io.i)
}
will generate this image: with the output of the register not being connected.

Also this:
case class DiagramDemo() extends Component {
  val io = new Bundle {
    val i = in port Bool()
    val i2 = in port Bool()
    val sel = in port Bool()
    val o = out port Bool()

    val i2b = in port Bits(2 bit)
    val muxout = out port Bool()

    val regout = out port Bool()
  }
  io.muxout := io.i2b.mux(
    0 -> (io.i & io.i2),
    1 -> (io.i | io.i2),
    2 -> (io.i ^ io.i2),
    3 -> (io.i)
  )
  io.regout := RegNextWhen(io.i, io.sel)
  io.o := False
  when(io.i) { io.o := True }
}
generates Where we see a similar thing with the outputs not being connected, and the assignments to io.o missing completely.

Nitpick: The blue on blue colorscheme of the examples above is kind of hard to read if you ask me.

PS: please also run scalafmt on the code.

I'm sorry for this silly bug. I accidentally deleted a pair of {} while removing the extra ones, which caused the program to produce incorrect results.I have fixed it and now the result is correct now.

I am a beginner in using Scala and there are some usages that I am not familiar with, which causes issues in my code writing. Thank you for your advice, I will carefully modify my program according to your suggestions.

ZhaokunHu · 2023-04-09T05:58:05Z

I have made modifications to the program and fixed some problems based on your suggestions .And I placed it in the spinal.lib.tools package. I have also added a test file which will generate an .html file.
I also add CDN link of HDElk to the HTML file so You won't have to place the js package in your project .You can simply just use your browser to open the HTML file and see the diagrams.

Readon · 2023-04-09T08:48:25Z

I have made modifications to the program and fixed some problems based on your suggestions .And I placed it in the spinal.lib.tools package. I have also added a test file which will generate an .html file. You will need to place the js package in https://github.com/davidthings/hdelk at the same directory as the HTML file, and then you can open the HTML file using a web browser.

This is an environment requirement. Just like we should install Quartus before we use Qsysnify.
As a library, SpinalHDL can only passively detect the environment but change it.
So it would be a way to have an environment variable "HDELK_PATH" which save the directory of required js files, thus it can be changed by user.

It's default value can be set as "https://github.com/davidthings/hdelk", so that if user is online no manual copy is required.
Or if we push the js file into SpinalHDL library, the default link could be "https://rawcontents.github.com/SpinalHDL/SpinalHDL/xxxxxx/hdelk".

Readon · 2023-04-09T10:19:59Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+         |		})
+         |	}
+         |</script>
+         |<script src="https://cdn.jsdelivr.net/gh/davidthings/hdelk@master/js/elk.bundled.js"></script>


This can be a default URL base, however, for users do not have network access might want to change this.
So use a variable is better here.:)

andreasWallner · 2023-04-10T11:07:30Z

I am a beginner in using Scala and there are some usages that I am not familiar with, which causes issues in my code writing. Thank you for your advice, I will carefully modify my program according to your suggestions.

No worries - stuff like that happens ;-)

I tested the latest version - the CDN links are much more comfortable than the local ones, but I agree with @Readon that it would be nice to have to option of passing an alternative path as a configuration.

I played around a bit more and stumbled over another small thing that's unexpected - it's cool that bundles are shown as a single signal, but accessing a signal from a bundle does not seem to get rendered/rendered incorrectly (test should be connected directly like testR is now, and testR should be connected to the FF?):

case class ElkDemo() extends Component {
  val io = new Bundle {
    val axii = slave port Axi4(Axi4Config(addressWidth=32, dataWidth=32, useId=false))
    val axio = master port Axi4(Axi4Config(addressWidth=32, dataWidth=32, useId=false))

    val test = out port Bool()
    val testR = out port Bool() setAsReg()
  }
  io.axii >> io.axio
  io.test := io.axii.r.valid
  io.testR := io.axii.w.valid
}

produces

add a new edge label. fix a bug.

ZhaokunHu · 2023-04-10T15:24:15Z

I am a beginner in using Scala and there are some usages that I am not familiar with, which causes issues in my code writing. Thank you for your advice, I will carefully modify my program according to your suggestions.

No worries - stuff like that happens ;-)

I tested the latest version - the CDN links are much more comfortable than the local ones, but I agree with @Readon that it would be nice to have to option of passing an alternative path as a configuration.

I played around a bit more and stumbled over another small thing that's unexpected - it's cool that bundles are shown as a single signal, but accessing a signal from a bundle does not seem to get rendered/rendered incorrectly (test should be connected directly like testR is now, and testR should be connected to the FF?):
case class ElkDemo() extends Component {
  val io = new Bundle {
    val axii = slave port Axi4(Axi4Config(addressWidth=32, dataWidth=32, useId=false))
    val axio = master port Axi4(Axi4Config(addressWidth=32, dataWidth=32, useId=false))

    val test = out port Bool()
    val testR = out port Bool() setAsReg()
  }
  io.axii >> io.axio
  io.test := io.axii.r.valid
  io.testR := io.axii.w.valid
}
produces

Thank you so much for testing for me! I have solved one bug. As for the signal testR，it is a little bit complex.Please give me some time to solve it.

at the latest version:

Add a new label for the edges which connect bus to one signal.
Using the writer instead of builder.
Change the page name to RTL diagrams of ${rtl.toplevelName}.

add colors to ports.

ZhaokunHu · 2023-04-11T08:27:43Z

Now the situation where the output port is also used as a register can be displayed correctly.

What's more, the color of the port has been added.

Readon · 2023-04-11T08:35:28Z

Now the situation where the output port is also used as a register can be displayed correctly.

What's more, the color of the port has been added.

Then, it's time to hide the clk & reset port, isn't it? :)

Readon · 2023-04-11T09:06:46Z

Maybe it would be good to use black as default node color, and just distinguish the clock domains by port color only?

wswslzp · 2023-04-11T14:33:47Z

Great job! It's really pleasant to see the first circuit diagram generator application building upon ModuleAnalyzer/DataAnalyzer (my apology for still not having doc for them).

Things so far look good to me but still, I have a little advice. From an architectural point of view, the generator is tightly coupled with the SpinalHDL internal data model. The process of data transformation is like SpinalHDL data model -> Elk HTML format. A better way to make things more scalable or extensible is to add a middle layer, such as SpinalHDL data model -> JSON -> Elk HTML. The middle JSON format serves as a module interface database that holds all the necessary information for the generator to draw the diagram.

There will be two benefits if a middle layer is introduced.

the generated interface database (e.g. a JSON file) can be reused by other tools which also need to elaborate the topology of the module.
your diagram generator can accept a universal format, not only for SpinalHDL. And this can be a more valuable open-source project.

Though, it's just a piece of advice and requires time and effort to reconstruct the project (I can see that it's nearly finished and not the early stage of the project). Thus, you can ignore my opinion and keep working. I'm very much looking forward to seeing the final product :)

Readon · 2023-04-11T15:50:18Z

Great job! It's really pleasant to see the first circuit diagram generator application building upon ModuleAnalyzer/DataAnalyzer (my apology for still not having doc for them).

Things so far look good to me but still, I have a little advice. From an architectural point of view, the generator is tightly coupled with the SpinalHDL internal data model. The process of data transformation is like SpinalHDL data model -> Elk HTML format. A better way to make things more scalable or extensible is to add a middle layer, such as SpinalHDL data model -> JSON -> Elk HTML. The middle JSON format serves as a module interface database that holds all the necessary information for the generator to draw the diagram.

There will be two benefits if a middle layer is introduced.

the generated interface database (e.g. a JSON file) can be reused by other tools which also need to elaborate the topology of the module.

your diagram generator can accept a universal format, not only for SpinalHDL. And this can be a more valuable open-source project.

Though, it's just a piece of advice and requires time and effort to reconstruct the project (I can see that it's nearly finished and not the early stage of the project). Thus, you can ignore my opinion and keep working. I'm very much looking forward to seeing the final product :)

Good idea!
Unfortunately, in this stage, it would be hard to archieve that.

Hdelk need to be modified to support json load function, whoes difficulty is still not investigated.
Zhaokun has a tight schedule on his under graduation report, so that it's not able to support a huge modifications now.
Maybe we could do that later.

There are still problems to be solved, as soon as we tried to draw diagram for Spinal cord or um, whose top level also contains amount of logic inside.

ZhaokunHu · 2023-04-12T04:37:00Z

Great job! It's really pleasant to see the first circuit diagram generator application building upon ModuleAnalyzer/DataAnalyzer (my apology for still not having doc for them).

Things so far look good to me but still, I have a little advice. From an architectural point of view, the generator is tightly coupled with the SpinalHDL internal data model. The process of data transformation is like SpinalHDL data model -> Elk HTML format. A better way to make things more scalable or extensible is to add a middle layer, such as SpinalHDL data model -> JSON -> Elk HTML. The middle JSON format serves as a module interface database that holds all the necessary information for the generator to draw the diagram.

There will be two benefits if a middle layer is introduced.

the generated interface database (e.g. a JSON file) can be reused by other tools which also need to elaborate the topology of the module.

your diagram generator can accept a universal format, not only for SpinalHDL. And this can be a more valuable open-source project.

Though, it's just a piece of advice and requires time and effort to reconstruct the project (I can see that it's nearly finished and not the early stage of the project). Thus, you can ignore my opinion and keep working. I'm very much looking forward to seeing the final product :)

I appreciate your PR very much. Without the ModuleAnalyzer/DataAnalyzer , this project would have been very difficult.

However, since this project relies heavily on the internal structure of SpinalHDL, it would be difficult to reconstruct to support a universal format. Additionally, I am not yet familiar enough with JSON and Scala, so I may not be able to complete the reconstruction. I apologize for not being able to accept your suggestion.

Readon · 2023-04-15T13:37:01Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

@@ -0,0 +1,552 @@
+package spinal.lib.tools
+
+


I think you should run scalafmt on this code to avoid fmt-lint reports.

Readon · 2023-04-15T13:37:38Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  /** Initializing data */
+  private val fileName = topLevelName + ".html"
+  private val file = new File(fileName)
+  private val pw = new FileWriter(file, true)


This pw could be named as writer?

Readon · 2023-04-15T13:39:25Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+    for (topInOut <- topInOuts) {
+      if (haveParent(topInOut)) {
+        val rootParent = findParent(topInOut)
+        if (rootParent.flatten.head.isInput) topNode.inPorts.add(ElkPort(rootParent.getName(),findPortHighlight(topInOut)))


How about use pattern match here?

Readon · 2023-04-15T13:40:48Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+    else if (allClk.size == 1) topNode.highlight = clkMap(allClk.head.toString())
+  }
+
+  private def GenAllNodes(): Unit = {


Maybe we should use a hierarchy class architecture to help to clean this logic.

Readon · 2023-04-15T13:41:36Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  }
+
+  private def GenAllEdges(): Unit = {
+    /** Getting the sonName of net */


This is really too big to look over.

Readon · 2023-04-15T13:44:59Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+    pw.write(s"""{id:"${thisNode.labelName}",\n""")
+    if (thisNode.typeName != "") pw.write(s"""type:"${thisNode.typeName}",\n""")
+    if (thisNode.highlight != 0) pw.write(s"""highlight:${thisNode.highlight},\n""")
+    if (thisNode.inPorts.nonEmpty) {


How about moving this logic into port specific class? so all related logic can be put into that.
Above code seems identical while it is in or out.

andreasWallner

A few comments of stuff that I observed. Most are suggestions that I think would make the code easier to read, some are small issues.
Keep up the good work!

andreasWallner · 2023-04-10T11:17:36Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+    val parentList = thisSon.getRefOwnersChain()
+    var returnParent = thisSon.parent
+    val loop = new Breaks
+    loop.breakable {


Instead of using breakable I'd could just return when you have found your parent, faster and IMHO easier to read

If you want to keep the breakable there is no need for the loop object in this case (since the breakable is not nested), you can

import Breaks.{breakable, break} breakable { // ... break // ... }

andreasWallner · 2023-04-10T11:26:24Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  }
+
+  private def haveRegParent(thisSon: BaseType): Boolean = {
+    var judge = false


Same as above, simple return true when you have found your answer - simpler to read and faster since it would stop iterating as soon as you know there is a Data
On another note: The function is called haveRegParent indicating that you are looking for a register, but you are never checking that the Data is a register?

andreasWallner · 2023-04-16T19:27:37Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+    val allClk = moduleAnalyze.getClocks
+    var clkCounter = 1
+    for (thisClk <- allClk) {
+      if (!clkMap.contains(thisClk.clock.getName())) {


Is there a specific reason why you are using the names in the dictionary instead of the signals themselves? Two CDs can actually have the same name...
Nitpick: clkMap is maybe a little bit misleading since you also add reset and softReset signals to the map

Using the name of the clock lead to this diagram:

For this code:

case class DiagramDemo() extends Component { val io = new Bundle { val i = in port Bool() val subo = out port Bool() val subo2 = out port Bool() } val sub = new Component { val i = in port Bool() val o = out port Bool() val myClockDomain = ClockDomain.external("clk") val coreArea = new ClockingArea(myClockDomain) { o := RegNext(i) } } val sub2 = new Component { val i = in port Bool() val o = out port Bool() val myClockDomain = ClockDomain.external("clk") val coreArea = new ClockingArea(myClockDomain) { o := RegNext(i) } } sub.i := io.i io.subo := sub.o sub2.i := io.i io.subo2 := sub2.o }

In reality this can happen when reusing multiple modules (that's why spinal internally only uses the name of the clock as a weak name, in the HDL the two are named clk_clk and clk_clk_1

Thank you for your reviews .They are very helpful .I have already made the changes for the other reviews, but I encountered some issues that I couldn't solve when dealing with this particular review. I was unable to obtain the necessary information to distinguish between two clock domains with the same name, so I have submitted an issue. #1090

andreasWallner · 2023-04-16T19:32:58Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  private val allInOuts = moduleAnalyze.getPins(_ => true)
+  private val everyRegisters = allRegisters ++ systemRegisters
+
+  private def haveParent(thisSon: BaseType): Boolean = {


Suggested change

private def haveParent(thisSon: BaseType): Boolean = {

private def hasParent(thisSon: BaseType): Boolean = {

andreasWallner · 2023-04-16T19:52:53Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  /** Generating the color mapping for clk */
+  private def GenColorMap(): Unit = {
+    val allClk = moduleAnalyze.getClocks
+    var clkCounter = 1


nit: you could skip counting here and use val clkCounter = clkMap.size + 2 inside the loop

andreasWallner · 2023-04-16T20:54:10Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+    }
+
+    for (topInOut <- topInOuts) {
+      if (haveParent(topInOut)) {


the code itself
If I understand correctly you are using findParent to find the bundle a signal is part of? And then after flattening it check the direction to see if the bundle is an input or output? If so then this code won't reliably work for IMasterSlave bundles since you are not guaranteed that head will reflect whether the bundle in a master (=output) or slave (=input).

case class Example() extends Bundle with IMasterSlave { val aa = Bool() val bb = Bool() def asMaster() = { in(aa) out(bb) } } case class DiagramDemo() extends Component { val io = new Bundle { val slave_port = slave port Example() val master_port = master port Example() } io.master_port <> io.slave_port }

generates:

(if it does not show for you, just swap in/out: out(aa) and in(bb))

repetition
The same (?) code is used just a few lines further down (176). Make a function that you call twice.

alternative implementation
I have observed that every time you use haveParent you also use findParent.
Consider changing findParent to return an Option[Data] and None if there is no parent. That would remove the need to loop through the signals twice.
Here you could then match...

andreasWallner · 2023-04-16T21:00:38Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+                returnParent = dataParent
+                loop.break()
+              } else {
+                dataParent.setName(


The diagrammer should not modify that data model of the HDL code.

andreasWallner · 2023-04-16T21:11:59Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  }
+
+  /** Integrating all methods to draw an image */
+  def beginDraw(): Unit = {


You should pass the writer as a parameter instead of opening it for append during construction and closing it here.

andreasWallner · 2023-04-16T21:15:02Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+  }
+
+  /** Generating HDElk language for Node */
+  private def drawNodes(thisNode: ElkNode): Unit = {


I'd move this code into the ElkNode

andreasWallner · 2023-04-16T21:16:17Z

lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala

+        }</button></a>&nbsp;\n""")
+    }
+    writer.write(s"""</div><br><br><br><br>\n""")
+    writer.close()


See above note about not opening/closing the writer multiple times. It should really only be opened once and then passed as a parameter.

Rebuilt some function.

delete tansprant color delete the clk

change the legend

ZhaokunHu · 2023-08-05T02:19:04Z

I have refactored my code. Please let me know if there are any shortcomings in terms of functionality and which parts of the code still need modification. I will do my best to make the necessary changes.

Dolu1990 · 2023-08-07T14:55:14Z

Hi ^^
I think it can be merged.

overall, maybe the issue currently is for none-small design.
maybe having some modes which :

omit combinatorial signal draw to keep things smaller (but keep connectivity done across them), so focussing on states
Preserve the Area structure / locality, but i guess this maybe not possible using HDElk ?
In some modes, we could even imagine that the diagram would "only" represent the connectivity between Area / sub component / io

One typical example could be recent reimplementation of the StreamFifo, which is now very much structured using Area

Change some judgement of bus.

ZhaokunHu · 2023-08-08T03:50:09Z

Hi ^^ I think it can be merged.

overall, maybe the issue currently is for none-small design. maybe having some modes which :

omit combinatorial signal draw to keep things smaller (but keep connectivity done across them), so focussing on states

Preserve the Area structure / locality, but i guess this maybe not possible using HDElk ?

In some modes, we could even imagine that the diagram would "only" represent the connectivity between Area / sub component / io

One typical example could be recent reimplementation of the StreamFifo, which is now very much structured using Area

Thank you for your suggestions.

I didn't fully understand what constitutes a combinatorial signal. To ensure the correct connectivity, I can only merge the nodes and edges instead of directly eliminating them. In the latest commit, I attempted some simplifications, but the results were only moderately successful.
2 & 3. Based on your suggestions, representing an Area in HDElk is indeed challenging. Additionally, it's difficult to differentiate signals within an Area as inputs or outputs. Therefore, I cannot add ports to the Area as I do for modules. One possible solution I can think of is to annotate the signal names connecting the Area's internal and external components, as shown in the diagram above.

Dolu1990 · 2023-08-08T07:05:55Z

Hi ^^

I didn't fully understand what constitutes a combinatorial signal

So i would say, in your screenshot above, combinatorial signals (stuff which isn't reg nor io) as for instance when_test12_l64, instead of being a box, could just represent connectivity.

it's difficult to differentiate signals within an Area as inputs or outputs

right :) something things are even mixed :/

ZhaokunHu · 2023-08-08T14:38:43Z

So i would say, in your screenshot above, combinatorial signals (stuff which isn't reg nor io) as for instance when_test12_l64, instead of being a box, could just represent connectivity.

Thank you again for your suggestions. ^^
I'm also eager to remove signals like "when_test12_l64"(stuff which isn't reg nor io) and have made some attempts in that direction.

Directly removing the node and converting it into a connection line is not feasible due to scenarios with multiple inputs and outputs, as illustrated in the diagram above.
Since converting this node into a connection isn't possible, I'm left with the option of renaming it. I've tried using reflection to access information defined within the code, aiming to replace the vague and ambiguous "when_test12_l64" label with the actual function names or conditions that the designer specified while writing the code. #1067 Unfortunately,due to my limited programming skills, I've been unable to successfully retrieve the desired information using reflection, and this idea remains unrealized.
As I lack the ability to implement this optimization myself, I may not be able to carry out this enhancement. :(

Readon · 2023-08-14T15:56:31Z

Hi ^^ I think it can be merged.

overall, maybe the issue currently is for none-small design. maybe having some modes which :

omit combinatorial signal draw to keep things smaller (but keep connectivity done across them), so focussing on states

Preserve the Area structure / locality, but i guess this maybe not possible using HDElk ?

In some modes, we could even imagine that the diagram would "only" represent the connectivity between Area / sub component / io

One typical example could be recent reimplementation of the StreamFifo, which is now very much structured using Area

I think we can merge this with a compatible API first. Then we could modify it if it is necessary later.

Add files via upload

e3a1745

ZhaokunHu closed this Apr 8, 2023

ZhaokunHu changed the title ~~Add files via upload~~ Generate diagrams based on SpinalHDL code Apr 8, 2023

ZhaokunHu reopened this Apr 8, 2023

Update GenerateDiagram.scala

d389de1

ZhaokunHu closed this Apr 8, 2023

ZhaokunHu added 2 commits April 8, 2023 20:03

Delete GenerateDiagram.scala

b568c9d

Add files via upload

f37adf3

ZhaokunHu reopened this Apr 8, 2023

andreasWallner reviewed Apr 8, 2023

View reviewed changes

Update GenerateDiagram.scala

59319db

Add Tester and Change the package.

f6932e3

Use cdn link to get the js package.

37757dd

Readon reviewed Apr 9, 2023

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using writer instead of builder.

77c717c

add a new edge label. fix a bug.

fix the connection bug.

dab6e2d

add colors to ports.

Readon reviewed Apr 15, 2023

View reviewed changes

Set the system-generated logical registers to transparent color.

d2d8f2c

andreasWallner reviewed Apr 16, 2023

View reviewed changes

ZhaokunHu mentioned this pull request Apr 19, 2023

Encountering Issues when Obtaining ClockDomains #1090

Closed

ZhaokunHu and others added 9 commits April 20, 2023 18:22

Fix the IMasterSlave bug.

746aac2

Rebuilt some function.

use ClockDomain object instead of name.

2974ddb

rebuild the HTMLGenerator

b7703b3

Merge branch 'dev' into GenerateDiagrams

945b13f

fix a small bug

88ee5df

Merge branch 'SpinalHDL:dev' into GenerateDiagrams

6a83979

rebuid the code

f0becc1

delete tansprant color delete the clk

change some clockDomains color

09ad31c

change the legend

change some name

08ab707

Add some edge labels for area.

fca56b2

Change some judgement of bus.

ZhaokunHu mentioned this pull request Aug 15, 2023

Add API description for HDElkDiagramGen SpinalHDL/SpinalDoc-RTD#206

Open

Merge branch 'dev' into GenerateDiagrams

e1e97cf

Readon merged commit 38149a8 into SpinalHDL:dev Aug 15, 2023
13 checks passed

	private def haveParent(thisSon: BaseType): Boolean = {
	private def hasParent(thisSon: BaseType): Boolean = {

Generate diagrams based on SpinalHDL code #1079

Generate diagrams based on SpinalHDL code #1079

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ZhaokunHu commented Aug 5, 2023

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