feature: add Jtag VPI support for sim #1095
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Btw. do you by any chance have an usage example somewhere online for trying it out? |
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not a complete one, but it is essentially a drop-in replacement for JtagTcp, like in Murax. An example openOCD config. If you want to test it with murax, you only need to change the JtagTcp line in the sim file, and change the cfg for openocd to the jtag_vpi interface with |
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When trying it here I stumbled over some minor things that I commented in the source. The thing is that I could not get it to work with Murax. (sorry it took me a bit since I had to recompile the spinal openocd fork, for some reason the one I had lying aroung did not support the vpi interface)
I tried by modifying MuraxSim from VexRiscv to use JtagVpi:
val jtagvpi = JtagVpi(dut.io.jtag, jtagClkPeriod=((12 MHz) / 4 ).toTime)instead of the JtagTcp it was using.
With the JtagTcp openocd/gdb worked as expected (command line src/openocd -f tcl/interface/jtag_tcp.cfg -c 'set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml' -f tcl/target/murax.cfg, that finds a device on the scanchain with ID 0x10001fff) but with JtagVpi I get errors (command line src/openocd -f tcl/interface/jtag_vpi.cfg -c 'set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml' -f tcl/target/murax.cfg).
% src/openocd -f tcl/interface/jtag_vpi.cfg -c 'set MURAX_CPU0_YAML ../VexRiscv/cpu0.yaml' -f tcl/target/murax.cfg
Open On-Chip Debugger 0.11.0+dev-04033-g058dfa50d (2023-04-24-01:20)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : jtag_vpi: server port set to 5555
Info : jtag_vpi: server address set to 127.0.0.1
../VexRiscv/cpu0.yaml
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter srst delay' not 'adapter_nsrst_delay'
Info : set servers polling period to 50ms
Info : jtag_vpi: Connection to 127.0.0.1 : 5555 successful
Info : This adapter doesn't support configurable speed
Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x20003fff (mfg: 0x7ff (<invalid>), part: 0x0003, ver: 0x2)
Warn : JTAG tap: fpga_spinal.bridge UNEXPECTED: 0x20003fff (mfg: 0x7ff (<invalid>), part: 0x0003, ver: 0x2)
Error: JTAG tap: fpga_spinal.bridge expected 1 of 1: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
Info : TAP auto0.tap does not have valid IDCODE (idcode=0xfffffffe)
Error: Trying to use configured scan chain anyway...
Error: fpga_spinal.bridge: IR capture error; saw 0x03 not 0x01
Warn : Bypassing JTAG setup events due to errors
Error: !!!
Error: Can't communicate with the CPU
Error: !!!
Kind of interesting might be that already the id of the device on the scanchain differs from the one I get via the JtagTcp interface.
Is there something in addition that I have to change to make it work?
| import spinal.lib.com.jtag.Jtag | ||
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| import java.nio.{ByteBuffer, ByteOrder} | ||
| import spinal.lib.com.jtag.sim.JtagDriver |
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No need for this import (since both files are in the same package once the package above is fixed), it actually generates a compile warning for me.
Suggested change
| import spinal.lib.com.jtag.sim.JtagDriver |
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In regard to your test, did you enable the jtag-vpi interface (is disabled by default by ./configure). to test it, I compiled the spinal fork and built with ` and then ran with It worked: Did you change anything else from sock in you configuration? the error you see looks like a misconfiguration of -irlen in the configuration (so all the bits are shifted by one) |
The changes that I did in Murax (tried with current VexRiscv master, c52433575dec04f10063b2fd7cebd0545c8b1be9): diff --git a/src/test/scala/vexriscv/MuraxSim.scala b/src/test/scala/vexriscv/MuraxSim.scala
index 6a6a19c..5fa1fd6 100644
--- a/src/test/scala/vexriscv/MuraxSim.scala
+++ b/src/test/scala/vexriscv/MuraxSim.scala
@@ -9,7 +9,7 @@ import spinal.core.sim._
import vexriscv.demo.{Murax, MuraxConfig}
import javax.swing._
-import spinal.lib.com.jtag.sim.JtagTcp
+import spinal.lib.com.jtag.sim.{JtagTcp, JtagVpi}
import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
import vexriscv.test.{JLedArray, JSwitchArray}
@@ -32,10 +32,11 @@ object MuraxSim {
clockDomain.forkStimulus(mainClkPeriod)
// clockDomain.forkSimSpeedPrinter(2)
- val tcpJtag = JtagTcp(
- jtag = dut.io.jtag,
- jtagClkPeriod = jtagClkPeriod
- )
+ //val tcpJtag = JtagTcp(
+ // jtag = dut.io.jtag,
+ // jtagClkPeriod = jtagClkPeriod
+ //)
+ val jtagvpi = JtagVpi(dut.io.jtag, jtagClkPeriod=((12 MHz) / 8).toTime)
val uartTx = UartDecoder(
uartPin = dut.io.uart.txd,With a val spinalVersion = "1.8.1"
lazy val spinalHdlIdslPlugin = ProjectRef(file("../SpinalHDL"), "idslplugin")
lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim")
lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core")
lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib")
lazy val root = (project in file(".")).
settings(
inThisBuild(List(
organization := "com.github.spinalhdl",
scalaVersion := "2.11.12",
version := "2.0.0"
)),
libraryDependencies ++= Seq(
"org.scalatest" %% "scalatest" % "3.2.5",
"org.yaml" % "snakeyaml" % "1.8"
),
name := "VexRiscv",
scalacOptions += (spinalHdlIdslPlugin / Compile / packageBin / artifactPath).map { file => s"-Xplugin:${file.getAbsolutePath}" }.value
).dependsOn(spinalHdlCore, spinalHdlLib, spinalHdlSim, spinalHdlIdslPlugin)
fork := trueI run it via OpenOCD (riscv_spinal branch, 058dfa50d625893bee9fecf8d604141911fac125): Gives: The log on a higher log level: |
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I just tried this in a clean docker, with no issues...: I just tried the same thing in a ubuntu docker, with all HEAD version and compiled: verilator, SpinalHDL/openocd_riscv, allexoll/SpinalHDL:jtag-vpi, SpinalHDL/Vexriscv, and no problem running it. can you give me the hash for the Spinal ref? |
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SpinalHDL ref is |
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If you need it there's a simple dockerfile as a basis, just need to clone and modify Vexriscv as you did before and test it with openocd: FROM ubuntu:22.04
ENV DEBIAN_FRONTEND=noninteractive
RUN apt-get update && apt-get install -y curl build-essential git perl gnupg2 python3 make help2man autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev libtool automake libusb-1.0.0-dev texinfo libusb-dev libyaml-dev pkg-config default-jdk scala verilator
#install SBT
RUN echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | tee /etc/apt/sources.list.d/sbt.list && \
echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | tee /etc/apt/sources.list.d/sbt_old.list && \
curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | apt-key add && \
apt-get update && \
apt-get install sbt
# conf sbt with more memory
ENV SBT_OPTS="-XX:+CMSClassUnloadingEnabled -Xmx4G -Xms4G"
RUN git clone https://github.com/SpinalHDL/openocd_riscv && \
cd openocd_riscv && \
./bootstrap && \
./configure --enable-jtag_pi && \
make -j && \
make install
RUN git clone https://github.com/allexoll/SpinalHDL && \
cd SpinalHDL && \
git checkout jtag-vpi && \
sbt clean publishLocal |
| tdoSeq(i) = jtag.tdo.toBoolean | ||
| doClockCycles(1) | ||
| } | ||
| tdoSeq.to[collection.immutable.Seq] |
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This can't work since the type parameters for Seq are missing
Suggested change
| tdoSeq.to[collection.immutable.Seq] | |
| tdoSeq.toSeq |
See also https://scastie.scala-lang.org/t1vaui2CR1qdlCtpZDfAFA
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that's weird, I do not get a warning on my setup, but I do get one with toSeq as it gives me a "remove redundant collection conversion"... would it make sense then to juste return tdoSeq?
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I tried with your Dockerfile but:
After those fixes it works in the resulting container. If you could have a look at the scala 2.13 comment above we can merge this I think (I figured out btw. why the CI doesn't complain, PR in the works :-) ) |
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Rebased this so that it runs in CI against all supported scala versions. |
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I think this is finally done... my editor still tells me that the "toSeq" is redundant, but since the CI is not complaining anymore, I'm fine with it as is... |
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Thanks so much! |
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thanks to you for dealing with all this! |
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Closes #
Context, Motivation & Description
This PR brings in some initial support for Jtag VPI, as an alternative to TcpJtag which require a forked openOCD. The VPI does not.
Impact on code generation
none
Checklist
/** */?