add setOutputAsReg

[KireinaHoro]

Similar to Data.setAsReg, but aware of the port direction that it only sets output ports as register. This allows a better shorthand like the following:

val io = new Bundle {
  val masterStream = master(Stream(Bits(4 bits))) setOutputAsReg()
}

Using setAsReg here would lead to the complaint of REGISTER DEFINED AS COMPONENT INPUT.

@Dolu1990 before merging, could you check if MultiData is the right place to put this function? Alternatively, should this be the default behaviour (if direction present, set as register only when is output) for setAsReg?

[KireinaHoro]

@Dolu1990 reimplemented setOutputAsReg in Data. So you think it's a good idea to keep this separate? (I don't know how to implement it in Data and merge it with setAsReg)

[Dolu1990]

So you think it's a good idea to keep this separate

Yes :)

All good, thanks !