inline literal input for some case

[yportne13]

commit 075e654 makes all the literal input not inline. this commit inline literal input for some case

[jijingg]

@yportne13 could you add some demo codes so that others can clearly handle what cases

[yportne13]

object TestInline extends App {
  SpinalVerilog(new Component{
    val sub = new Component {
      val x = in Bits(1 bits)
    }
    sub.x.setAll()
  })
}

origin:

module unamed_1 (
);

  wire       [0:0]    sub_x;

  unamed sub (
    .x (sub_x)  //i
  );
  assign sub_x = 1'b1;

endmodule

this commit:

module unamed_1 (
);


  unamed sub (
    .x (1'b1)  //i
  );

endmodule