SynthesisBench cleaning/experiments

SpinalHDL · Feb 11, 2018 · 3853e03 · 3853e03
1 parent 2a336c2
commit 3853e03
Showing 1 changed file with 35 additions and 12 deletions.
diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala
@@ -1,62 +1,85 @@
 package vexriscv.demo
 
-import spinal.core.SpinalVerilog
-import spinal.lib.eda.bench.{XilinxStdTargets, Bench, AlteraStdTargets, Rtl}
+import spinal.core._
+import spinal.lib.eda.bench._
+
+import scala.collection.mutable.ArrayBuffer
 
 /**
  * Created by PIC32F_USER on 16/07/2017.
  */
 object VexRiscvSynthesisBench {
   def main(args: Array[String]) {
+
+    def wrap(that : => Component) : Component = that
+    //Wrap with input/output registers
+    //    def wrap(that : => Component) : Component = {
+    //      //new WrapWithReg.Wrapper(that)
+    //      val c = that
+    //      c.rework {
+    //        for (e <- c.getOrdredNodeIo) {
+    //          if (e.isInput) {
+    //            e.asDirectionLess()
+    //            e := RegNext(RegNext(in(cloneOf(e))))
+    //
+    //          } else {
+    //            e.asDirectionLess()
+    //            out(cloneOf(e)) := RegNext(RegNext(e))
+    //          }
+    //        }
+    //      }
+    //      c
+    //    }
+
     val smallestNoCsr = new Rtl {
       override def getName(): String = "VexRiscv smallest no CSR"
       override def getRtlPath(): String = "VexRiscvSmallestNoCsr.v"
-      SpinalVerilog(GenSmallestNoCsr.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenSmallestNoCsr.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
     val smallest = new Rtl {
       override def getName(): String = "VexRiscv smallest"
       override def getRtlPath(): String = "VexRiscvSmallest.v"
-      SpinalVerilog(GenSmallest.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenSmallest.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
     val smallAndProductive = new Rtl {
       override def getName(): String = "VexRiscv small and productive"
       override def getRtlPath(): String = "VexRiscvSmallAndProductive.v"
-      SpinalVerilog(GenSmallAndProductive.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenSmallAndProductive.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
     val fullNoMmuNoCache = new Rtl {
       override def getName(): String = "VexRiscv full no MMU no cache"
       override def getRtlPath(): String = "VexRiscvFullNoMmuNoCache.v"
-      SpinalVerilog(GenFullNoMmuNoCache.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenFullNoMmuNoCache.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
     val fullNoMmu = new Rtl {
       override def getName(): String = "VexRiscv full no MMU"
       override def getRtlPath(): String = "VexRiscvFullNoMmu.v"
-      SpinalVerilog(GenFullNoMmu.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenFullNoMmu.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
     val noCacheNoMmuMaxPerf= new Rtl {
       override def getName(): String = "VexRiscv no cache no MMU max perf"
       override def getRtlPath(): String = "VexRiscvNoCacheNoMmuMaxPerf.v"
-      SpinalVerilog(GenNoCacheNoMmuMaxPerf.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenNoCacheNoMmuMaxPerf.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
     val fullNoMmuMaxPerf= new Rtl {
       override def getName(): String = "VexRiscv full no MMU max perf"
       override def getRtlPath(): String = "VexRiscvFullNoMmuMaxPerf.v"
-      SpinalVerilog(GenFullNoMmuMaxPerf.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenFullNoMmuMaxPerf.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
     val full = new Rtl {
       override def getName(): String = "VexRiscv full"
       override def getRtlPath(): String = "VexRiscvFull.v"
-      SpinalVerilog(GenFull.cpu().setDefinitionName(getRtlPath().split("\\.").head))
+      SpinalVerilog(wrap(GenFull.cpu()).setDefinitionName(getRtlPath().split("\\.").head))
     }
 
-//    val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
-    val rtls = List(noCacheNoMmuMaxPerf, fullNoMmuMaxPerf)
+    val rtls = List(smallestNoCsr, smallest, smallAndProductive, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
+   // val rtls = List(noCacheNoMmuMaxPerf, fullNoMmuMaxPerf)
 
     val targets = XilinxStdTargets(
       vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"