Merge pull request #399 from martijnbastiaan/wishbone-err

Handle `ERR` in `toWishbone`
SpinalHDL · Mar 29, 2024 · 457ae5c · 457ae5c
2 parents 6aeb6d4 + 5f58e0c
commit 457ae5c
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Showing 4 changed files with 13 additions and 13 deletions.
diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -368,13 +368,13 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
     bus.WE  := cmdBridge.wr
     bus.DAT_MOSI := cmdBridge.data
 
-    cmdBridge.ready := cmdBridge.valid && bus.ACK
+    cmdBridge.ready := cmdBridge.valid && (bus.ACK || bus.ERR)
     bus.CYC := cmdBridge.valid
     bus.STB := cmdBridge.valid
 
-    rsp.valid := RegNext(cmdBridge.valid && !bus.WE && bus.ACK) init(False)
+    rsp.valid := RegNext(cmdBridge.valid && !bus.WE && (bus.ACK || bus.ERR)) init(False)
     rsp.data  := RegNext(bus.DAT_MISO)
-    rsp.error := False //TODO
+    rsp.error := RegNext(bus.ERR)
     bus
   }
 

diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -239,15 +239,15 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
     when(cmd.valid || pending){
       bus.CYC := True
       bus.STB := True
-      when(bus.ACK){
+      when(bus.ACK || bus.ERR){
         counter := counter + 1
       }
     }
 
-    cmd.ready := cmd.valid && bus.ACK
-    rsp.valid := RegNext(bus.CYC && bus.ACK) init(False)
+    cmd.ready := cmd.valid && (bus.ACK || bus.ERR)
+    rsp.valid := RegNext(bus.CYC && (bus.ACK || bus.ERR)) init(False)
     rsp.data := RegNext(bus.DAT_MISO)
-    rsp.error := False //TODO
+    rsp.error := RegNext(bus.ERR)
     bus
   }
 

diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -199,13 +199,13 @@ case class DBusSimpleBus(bigEndian : Boolean = false) extends Bundle with IMaste
     bus.WE  := cmdStage.wr
     bus.DAT_MOSI := cmdStage.data
 
-    cmdStage.ready := cmdStage.valid && bus.ACK
+    cmdStage.ready := cmdStage.valid && (bus.ACK || bus.ERR)
     bus.CYC := cmdStage.valid
     bus.STB := cmdStage.valid
 
-    rsp.ready := cmdStage.valid && !bus.WE && bus.ACK
+    rsp.ready := cmdStage.valid && !bus.WE && (bus.ACK || bus.ERR)
     rsp.data  := bus.DAT_MISO
-    rsp.error := False //TODO
+    rsp.error := bus.ERR
     bus
   }
 

diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
@@ -156,10 +156,10 @@ case class IBusSimpleBus(plugin: IBusSimplePlugin) extends Bundle with IMasterSl
     bus.STB := cmdPipe.valid
 
 
-    cmdPipe.ready := cmdPipe.valid && bus.ACK
-    rsp.valid := bus.CYC && bus.ACK
+    cmdPipe.ready := cmdPipe.valid && (bus.ACK || bus.ERR)
+    rsp.valid := bus.CYC && (bus.ACK || bus.ERR)
     rsp.inst := bus.DAT_MISO
-    rsp.error := False //TODO
+    rsp.error := bus.ERR
     bus
   }