VexRiscvSmpCluster add more debug trigger options

SpinalHDL · Mar 5, 2024 · 7812bc6 · 7812bc6
1 parent 1943b25
commit 7812bc6
Showing 1 changed file with 9 additions and 2 deletions.
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -255,7 +255,9 @@ object VexRiscvSmpClusterGen {
                      withInstructionCache : Boolean = true,
                      forceMisa : Boolean = false,
                      forceMscratch : Boolean = false,
-                     privilegedDebug : Boolean = false,
+                     privilegedDebug: Boolean = false,
+                     privilegedDebugTriggers: Int = 2,
+                     privilegedDebugTriggersLsu: Boolean = false,
                      csrFull : Boolean = false
                     ) = {
     assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
@@ -264,7 +266,12 @@ object VexRiscvSmpClusterGen {
 
     val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "s" else ""}")
     val csrConfig = if(withSupervisor){
-      var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(utimeAccess = CsrAccess.READ_ONLY, withPrivilegedDebug = privilegedDebug)
+      var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(
+        utimeAccess = CsrAccess.READ_ONLY,
+        withPrivilegedDebug = privilegedDebug,
+        debugTriggers = privilegedDebugTriggers,
+        debugTriggersLsu = privilegedDebugTriggersLsu
+      )
       if(csrFull){
        c = c.copy(
          mcauseAccess   = CsrAccess.READ_WRITE,