Contents

Day 1: Inception of Open Source EDA ,OpenLane sky130PDK

• Introduction
• Physical Design
• Familiar with Openslane
• Openlane ASIC flow

Day2 : Floorplan and Introduction to library Cells

• Floorplan
• AspectRatio
• Preplaced cells
• Decoupling Capacitors

Day 3: Library Cell design using Magic layout and Characterisation of Library Cell

• CMOS inverter ngspice simulations
• CMOS Fabrication Process
• Inception of Layout
• Sky130A tech File Labs

Day 4 : Pre-layout timing analysis and importance of good clock tree

• Delay tables and Timing Models
• ClockTreeSynthesis (CTS) using TritonCTS
• Timing Analysis using OpenSTA

Day 5: Routing and Power Distribution

• Lee_Maze Routing Algorithm
• Power Distribution
• Triton Route Features

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Day 1 :Inception of Open Source EDA ,OpenLane sky130PDK

Introduction

• Integrated circuit is the one in which thousand of gates ,resistors and capacitors are fabricated into it.An IC act as a memory,timer,counter ,amplifier etc.The main advantage of Ic is they are small in size and when comes to the functionality they does the best job.They are availabel in the form of packages.

In the above figure IP represents the Intellectual Property (IP) which are specific foundary. RISC V ,SRAM are the macros which are placed inside core.In the area surrounding the core I/O cells are placed. Physical design is the step which is used to place Intellectual Property (IP) and macros inside the core area.

Physical design

• Physical is the process of converting the circuit description which is written in HDL(Hardware Description Language) into a physical layout.It consists of different stages
• Floorplan : In this macros are placed in the core area.
• Placement :In this standard cells are placed.
• Clock Tree Synthesis: In this clock tree is built.
• Routing: In this interconnections are made using metal layerrs and vias. The IC communicates with hardware and the software .The system software converts the software language into assembly language which is the language understand by the IC and this way the required functionality is performed.

OpenLane ASIC Flow

• Openlane is an automated pandR tool which performs the RTS to GDS11 flow.

• In order to invoke the design we use the following commands Linux terminal use docker commnad use ./flow.tcl -interactive

Use the command prep -design design_name trial_run -overwrite

• The percentage number of flops are obtained by dividing number of flops by total number of cells

Synthesis : Synthesis is the process of converting RTL code to optimised gate level netlist.It is obtained by using following command run_synthesis

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Day2 : Floorplan and Introduction to library Cells

Floorplan

• It is the first step in the physical design.The quality of floorplan will decide the chip performance .It is the process of placing macros in the core area. It determines the size of the die and create wire tracks for placement of standard cells.
• Core :
• It is defined as the inner block which contains the std cells and macros.
• Die:
• It is the block around the core which contains i/o ports.
• Aspect Ratio:
• It wiil decide the size and shape of the chip.It is the ratio of vertical routing resources to the horizontal routing resources.If its value is 1 then it is of square shape and if it is greater than 1 then it is of rectangular shape.

Aspect Ratio = Height / Width

• Core Utilisation: *It defines the area occupied by macros,standard cells and other cells.If Core utilisation is 70% that means 70% of core area is use for placing the standard cells,macros and other cells and remaining 30% is for routing.In other words it is the area occupied by the netlist.

Utilisation factor= Area occupied by the netlist /Total area of the core.

Preplaced cells:

• These have user defined locationa and hence placed in chip before automated before automated placement and routing and this type of cells are called preplaced cells.Once they are placed on the core area they are not moved by any automated tools and the are fixed.Some of preplaced cells are mux,flipflop and comparator etc.

Decoupling Capacitors:

• In order to protect the cells from the disturbances which occur in power supply deccouplig Capcitors are used.It is better to surround the macros using decoupling capacitors which are generally called as decap cells.

Power Planning :

• The power planning is done in this stage. The power has to be distributed equally to all macros and standard cells using power network.

Pin Placement:

• The pins are placed around the core.Clock ports are bigger in size when compared to other ports.Backend people decide the pin placement in Pnr flow.

• The floorplan is run by using the following command

run_floorplan

• The layout of the floorplan obtained can be seen by using following command magic -T

• To run placement use the following command

run_placement

The standard cells can be seen by zooming the layout i.e., by select and press z.

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Day 3: Library Cell design using Magic layout and Characterisation of Library Cell

Spice deck

• Spice deck is the one which gives information regarding the connectivity of components.In other words we can call this as netlist.

Component values

• The components which are used are PMOS and NMOS.The width and length value of these play an important role in determining the output. The W and L values of PMOS and NMOS respectively are

M1:PMOS W/L=0.375u / 0.25 M2 :NOMS W/L=0.375u / 0.25u

Node

• A Node is a point where in between component is present. Node is a positive number starting from 0 to n.It can be either vdd,gnd,in,out. The Model parameters and netlist description of PMOS and NMOS are as follows PMOS: Pre-layout and post-layout simulation
• M1 out in Vdd Vdd pmos W=0.375u L=0.25u The above M1 represents PMOS which is connected in the specified order of drain gate source substrate. NMOS:
• M2 out in 0 0 nmos W=0.375u L=0.25u The above M1 represents NMOS which is connected in the specified order of drain gate source substrate.
• Cload out 0 10f Here the load capacitor connected between the out and 0 node having a value of 10fF is specified in the above spice statement.
• Vdd vdd 0 2.5 Here also the power supply Vdd is connected between the vdd and 0 nodes and has value 2.5V is specified in the above spice statement. Vin in 0 2.5 Commands for simulating CMOS inverter
• The following represents the commands for simulating spice model of CMOS inverter
• .op
• .dc Vin 0 2.5 0.05
• The spice which are mentioned above are used to sweep input voltage from 0 to 2.5v in steps of 0.05v to get the output voltage. The following represents the cases of PMOS and NMOS where there is variation in waveform
• When, Wn = Wp = 0.375u and Ln,p = 0.25u - The (W/L)n = (W/L)p = 1.5
• The VTC Curve is shifted towards the left and the switching threshold Vm = 0.98 V
• When, Wn = 0.375u, Wp= 0.9375 ( observe that Wp = 2.5 * Wn )
• The VTC Curve is exactly at the middle , and the switching threshold Vm = 1.2 V
• Hence we can observe the transfer characteristics of CMOS inverter are as follows

Layout of CMOS inverter

• The layout is drawn taking the connectivity information from netlist and Euler path has to be taken into consideration.The DRC rules have to be considered for drawing a layout.DRC is a foundary document which gives information about spacing,extension,overlap,contact size etc. CMOS Inverter characterisation

• The characterisation of Inverter depends upon the following factors

• Derive actual dimensions for the function

• Script to create layout in Magic

• Final layout and input output *

• The standard cell library is obtained into our design by cloning git repository

• The git link is as follows

• https://github.com/nickson-jose/vsdstdcelldesign.git

• The tech file is copied using cp command

• The layout preview is obtained by using the below command

*For central view of inverter layout press s and then v

• By using extract all an extracted file is generated.

• By using ext2spice spice netlist is generated.

• The extracted file is as below

• Modify using Escape+i

• The modified spice netlist is as below

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Day 4 : Pre-layout timing analysis and importance of good clock tree

Setup time: The time interval for which the data has to be stable before the clock edge is called setup time.

Hold time :The time interval for which the data has to be stable after the clock edge is called hold time.

Skew: The difference in the arrival of clock from clock source to clock pin of flipflops.The skew has to be as minimum as possible.Practically zero skew is not possible.

Latency :The amount of time taken to travel from clock source to clock definition point.

Clock Jitter: The variation of clock edge from the ideal clock edge is called jitter.It is modelled by using clock uncerrtainity.

Clock Tree Synthesis: CTS is the process of building the clock tree. Buffers and inverters are used for building the clock tree.The main aim of CTS is to minimise the clock skew.

When u press g reference cell can be seen.

The information regarding tracks is present in the track file which is mentioned below

The modified config.tcl is as below . It is modified using Esc+i.

Since the slack is met change the strategy of synthesis, buffering, sizing to reduce the slack violations and run synthesis again.

After synthesis

run_placement

Day 5: Routing and Power Distribution

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Routing : The process of interconnecting the metal wire to all the cells i.e., Macros,stdcells which are present in the core. Electrical connections using metals and vias are created in the layout, defined by the logical connections which are present in the netlist.Connections are made using vias for different metals.The main goal of routing is to reduce the total interconnect length.
Routing is of two types

Global Routing:

• In Global Routing we dont do the actaul connections.The approximate interconnections between the blocks are made in this.In other words it just plan the connections .

Detailed Routing:

• Detailed routing takes information from global routing and does the actual interconnection between the cells.

Lees Algorithm

• This is most widely used algorithm to find the path between two points.In this algorithm the cells between which the path has to be made are identified One cell is made target and other cell is made source. Routing grids are drawn on the chip .Numbering is done for the grid box surrounding the cells.One has to continue to number the grid until target cell is reached. Based on this numbering the path is decided from source to target. Generally L shape routing is preferred. The main disadvantage of this algorithm is it consumes large amount of memory and time.

• The Command which used for routing is as below. Openlane uses Triton Route to do routing

run_routing

Power Distribution

• It is the process of distributing the power(VDD and VSS) to all macros and standard cells which are present in the core.The power is distributed using rails,rings,straps.

• Rails : The rails will connect VDD and VSS to std cells.

• Rings : Ring is the one which is placed around the chip which Carries VDD and VSS.

• Straps :Since it is difficult to transfer power equally from edge of the chip to centre of the chip .We use vertical and horizontal nets in the chip from the rings to carry power.

• The command which is used for generating power is as below

``gen_pdn

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Acknoweledge

Kunal Ghosh , Co-founder (VSD Corp. Pvt. Ltd).

Nickson Jose , VSD VLSI Engineer

Mansi Mahapatar VSD TA

MiliAnand VSD TA