Remove tb_file between tests

tests/test_pe.py

@@ -91,6 +91,14 @@ def rtl_tester(test_op, data0=None, data1=None, bit0=None, bit1=None, bit2=None,
         for filename in libs:
             copy_file(os.path.join(cw_dir, filename),
                       os.path.join(test_dir, filename))
+        # Seeing a strange issue where ncsim doesn't always recompile between
+        # tests with a new test bench, because we know for every new system
+        # verilog test bench that we'll have a new `_tb` file, we just nuke it
+        # here now to force ncsim to recompile
+        # See https://github.com/StanfordAHA/lassen/issues/111 for more info
+        tb_file = os.path.join(test_dir, f"{pe_circuit.name}_tb.sv")
+        if os.path.exists(tb_file):
+            os.remove(tb_file)
         tester.compile_and_run(target="system-verilog", simulator="ncsim",
                                directory="tests/build/",
                                include_verilog_libraries=libs,