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virt86 1.1.0

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@StrikerX3 StrikerX3 released this 01 Jul 22:00
· 12 commits to master since this release
v1.1.0
e3226d6

Version 1.1.0 contains breaking changes to gdt.hpp. GDTEntry is now an union containing various types of GDT entries. Existing code should now check the type of GDT entry via <GDTEntry value>.generic.system and drill down depending on the type. See VirtualProcessor::GetGDTEntry for more details on how to determine the GDT entry type and how to read their values. Additionally, the codeDataSegment field was renamed to system to better reflect its actual meaning.

GDT entry handling received these fixes:

  • LDT and TSS entries are expanded to 16 bytes in IA-32e mode. The new code now reads them correctly, as well as call gates, task gates, interrupt gates and trap gates, in addition to regular GDT entries, of course.
  • VirtualProcessor::ReadSegment now validates the entries and can load LDT and TSS correctly. Since gates cannot be loaded into segment registers, they will not be read into the RegValue variable.

This version also brings the following improvements:

  • virt86 now detects the maximum supported guest physical address on the host and prevents mapping memory to guests beyond the allowed range.
    • HAXM (as of 7.5.1) further restricts the maximum GPA address range to 231 pages.
  • Floating point extensions supported by the host are now identified via cpuid. Virtualization platforms may further restrict the supported extension set in their guests.
    • HAXM (as of 7.5.1) does not handle the VM exit caused by xsetbv and therefore does not support AVX. All AVX-related extensions are thus disabled with this platform.
  • WHPX adapter will now detect the platform version running on the host system and selectively enable certain features according to the version:
    • 10.0.17763.0: XCR0 register, SPEC_CTRL and PRED_CMD MSRs and dirty bitmap support.
  • WHPX should now initialize correctly on Windows 10 systems with platform version 10.0.17134.0.
  • Floating point registers beyond the first of each type (e.g. ST1, MM5, XMM15) should now read and write correctly on all platforms.
  • Defined FXSAVE and XSAVE data structures, including all known XSAVE components.
  • Fixed CPUID leaf handling with KVM which caused guests to not detect advanced CPU features properly.
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