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codegenarm64.cpp
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codegenarm64.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Arm64 Code Generator XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef TARGET_ARM64
#include "emit.h"
#include "codegen.h"
#include "lower.h"
#include "gcinfo.h"
#include "gcinfoencoder.h"
#include "patchpointinfo.h"
/*
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Prolog / Epilog XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
void CodeGen::genPopCalleeSavedRegistersAndFreeLclFrame(bool jmpEpilog)
{
assert(compiler->compGeneratingEpilog);
regMaskTP rsRestoreRegs = regSet.rsGetModifiedRegsMask() & RBM_CALLEE_SAVED;
if (isFramePointerUsed())
{
rsRestoreRegs |= RBM_FPBASE;
}
rsRestoreRegs |= RBM_LR; // We must save/restore the return address (in the LR register)
regMaskTP regsToRestoreMask = rsRestoreRegs;
const int totalFrameSize = genTotalFrameSize();
// Fetch info about the frame we saved when creating the prolog.
//
const int frameType = compiler->compFrameInfo.frameType;
const int calleeSaveSpOffset = compiler->compFrameInfo.calleeSaveSpOffset;
const int calleeSaveSpDelta = compiler->compFrameInfo.calleeSaveSpDelta;
const int offsetSpToSavedFp = compiler->compFrameInfo.offsetSpToSavedFp;
switch (frameType)
{
case 1:
{
JITDUMP("Frame type 1. #outsz=0; #framesz=%d; localloc? %s\n", totalFrameSize,
dspBool(compiler->compLocallocUsed));
if (compiler->compLocallocUsed)
{
// Restore sp from fp
// mov sp, fp
inst_Mov(TYP_I_IMPL, REG_SPBASE, REG_FPBASE, /* canSkip */ false);
compiler->unwindSetFrameReg(REG_FPBASE, 0);
}
regsToRestoreMask &= ~(RBM_FP | RBM_LR); // We'll restore FP/LR at the end, and post-index SP.
break;
}
case 2:
{
JITDUMP("Frame type 2 (save FP/LR at bottom). #outsz=%d; #framesz=%d; localloc? %s\n",
unsigned(compiler->lvaOutgoingArgSpaceSize), totalFrameSize, dspBool(compiler->compLocallocUsed));
assert(!genSaveFpLrWithAllCalleeSavedRegisters);
if (compiler->compLocallocUsed)
{
// Restore sp from fp
// sub sp, fp, #outsz // Uses #outsz if FP/LR stored at bottom
int SPtoFPdelta = genSPtoFPdelta();
GetEmitter()->emitIns_R_R_I(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_FPBASE, SPtoFPdelta);
compiler->unwindSetFrameReg(REG_FPBASE, SPtoFPdelta);
}
regsToRestoreMask &= ~(RBM_FP | RBM_LR); // We'll restore FP/LR at the end, and post-index SP.
break;
}
case 3:
{
JITDUMP("Frame type 3 (save FP/LR at bottom). #outsz=%d; #framesz=%d; localloc? %s\n",
unsigned(compiler->lvaOutgoingArgSpaceSize), totalFrameSize, dspBool(compiler->compLocallocUsed));
assert(!genSaveFpLrWithAllCalleeSavedRegisters);
JITDUMP(" calleeSaveSpDelta=%d\n", calleeSaveSpDelta);
regsToRestoreMask &= ~(RBM_FP | RBM_LR); // We'll restore FP/LR at the end, and (hopefully) post-index SP.
int remainingFrameSz = totalFrameSize - calleeSaveSpDelta;
assert(remainingFrameSz > 0);
if (compiler->lvaOutgoingArgSpaceSize > 504)
{
// We can't do "ldp fp,lr,[sp,#outsz]" because #outsz is too big.
// If compiler->lvaOutgoingArgSpaceSize is not aligned, we need to align the SP adjustment.
assert(remainingFrameSz > (int)compiler->lvaOutgoingArgSpaceSize);
int spAdjustment2Unaligned = remainingFrameSz - compiler->lvaOutgoingArgSpaceSize;
int spAdjustment2 = (int)roundUp((unsigned)spAdjustment2Unaligned, STACK_ALIGN);
int alignmentAdjustment2 = spAdjustment2 - spAdjustment2Unaligned;
assert((alignmentAdjustment2 == 0) || (alignmentAdjustment2 == REGSIZE_BYTES));
// Restore sp from fp. No need to update sp after this since we've set up fp before adjusting sp
// in prolog.
// sub sp, fp, #alignmentAdjustment2
GetEmitter()->emitIns_R_R_I(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_FPBASE, alignmentAdjustment2);
compiler->unwindSetFrameReg(REG_FPBASE, alignmentAdjustment2);
// Generate:
// ldp fp,lr,[sp]
// add sp,sp,#remainingFrameSz
JITDUMP(" alignmentAdjustment2=%d\n", alignmentAdjustment2);
genEpilogRestoreRegPair(REG_FP, REG_LR, alignmentAdjustment2, spAdjustment2, false, REG_IP1, nullptr);
}
else
{
if (compiler->compLocallocUsed)
{
// Restore sp from fp; here that's #outsz from SP
// sub sp, fp, #outsz
int SPtoFPdelta = genSPtoFPdelta();
assert(SPtoFPdelta == (int)compiler->lvaOutgoingArgSpaceSize);
GetEmitter()->emitIns_R_R_I(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_FPBASE, SPtoFPdelta);
compiler->unwindSetFrameReg(REG_FPBASE, SPtoFPdelta);
}
// Generate:
// ldp fp,lr,[sp,#outsz]
// add sp,sp,#remainingFrameSz ; might need to load this constant in a scratch register if
// ; it's large
JITDUMP(" remainingFrameSz=%d\n", remainingFrameSz);
genEpilogRestoreRegPair(REG_FP, REG_LR, compiler->lvaOutgoingArgSpaceSize, remainingFrameSz, false,
REG_IP1, nullptr);
}
// Unlike frameType=1 or frameType=2 that restore SP at the end,
// frameType=3 already adjusted SP above to delete local frame.
// There is at most one alignment slot between SP and where we store the callee-saved registers.
assert((calleeSaveSpOffset == 0) || (calleeSaveSpOffset == REGSIZE_BYTES));
break;
}
case 4:
{
JITDUMP("Frame type 4 (save FP/LR at top). #outsz=%d; #framesz=%d; localloc? %s\n",
unsigned(compiler->lvaOutgoingArgSpaceSize), totalFrameSize, dspBool(compiler->compLocallocUsed));
assert(genSaveFpLrWithAllCalleeSavedRegisters);
if (compiler->compLocallocUsed)
{
// Restore sp from fp
// sub sp, fp, #outsz // Uses #outsz if FP/LR stored at bottom
int SPtoFPdelta = genSPtoFPdelta();
GetEmitter()->emitIns_R_R_I(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_FPBASE, SPtoFPdelta);
compiler->unwindSetFrameReg(REG_FPBASE, SPtoFPdelta);
}
break;
}
case 5:
{
JITDUMP("Frame type 5 (save FP/LR at top). #outsz=%d; #framesz=%d; localloc? %s\n",
unsigned(compiler->lvaOutgoingArgSpaceSize), totalFrameSize, dspBool(compiler->compLocallocUsed));
assert(genSaveFpLrWithAllCalleeSavedRegisters);
assert((calleeSaveSpOffset == 0) || (calleeSaveSpOffset == REGSIZE_BYTES));
// Restore sp from fp:
// sub sp, fp, #sp-to-fp-delta
// This is the same whether there is localloc or not. Note that we don't need to do anything to remove the
// "remainingFrameSz" to reverse the SUB of that amount in the prolog.
GetEmitter()->emitIns_R_R_I(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_FPBASE, offsetSpToSavedFp);
compiler->unwindSetFrameReg(REG_FPBASE, offsetSpToSavedFp);
break;
}
default:
unreached();
}
JITDUMP(" calleeSaveSpOffset=%d, calleeSaveSpDelta=%d\n", calleeSaveSpOffset, calleeSaveSpDelta);
genRestoreCalleeSavedRegistersHelp(regsToRestoreMask, calleeSaveSpOffset, calleeSaveSpDelta);
switch (frameType)
{
case 1:
{
// Generate:
// ldp fp,lr,[sp],#framesz
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, REG_FP, REG_LR, REG_SPBASE, totalFrameSize,
INS_OPTS_POST_INDEX);
compiler->unwindSaveRegPairPreindexed(REG_FP, REG_LR, -totalFrameSize);
break;
}
case 2:
{
// Generate:
// ldp fp,lr,[sp,#outsz]
// add sp,sp,#framesz
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, REG_FP, REG_LR, REG_SPBASE,
compiler->lvaOutgoingArgSpaceSize);
compiler->unwindSaveRegPair(REG_FP, REG_LR, compiler->lvaOutgoingArgSpaceSize);
GetEmitter()->emitIns_R_R_I(INS_add, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, totalFrameSize);
compiler->unwindAllocStack(totalFrameSize);
break;
}
case 3:
case 4:
case 5:
{
// Nothing to do after restoring callee-saved registers.
break;
}
default:
{
unreached();
}
}
// For OSR, we must also adjust the SP to remove the Tier0 frame.
//
if (compiler->opts.IsOSR())
{
PatchpointInfo* const patchpointInfo = compiler->info.compPatchpointInfo;
const int tier0FrameSize = patchpointInfo->TotalFrameSize();
JITDUMP("Extra SP adjust for OSR to pop off Tier0 frame: %d bytes\n", tier0FrameSize);
// Tier0 size may exceed simple immediate. We're in the epilog so not clear if we can
// use a scratch reg. So just do two subtracts if necessary.
//
int spAdjust = tier0FrameSize;
if (!GetEmitter()->emitIns_valid_imm_for_add(tier0FrameSize, EA_PTRSIZE))
{
const int lowPart = spAdjust & 0xFFF;
const int highPart = spAdjust - lowPart;
assert(GetEmitter()->emitIns_valid_imm_for_add(highPart, EA_PTRSIZE));
GetEmitter()->emitIns_R_R_I(INS_add, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, highPart);
compiler->unwindAllocStack(highPart);
spAdjust = lowPart;
}
assert(GetEmitter()->emitIns_valid_imm_for_add(spAdjust, EA_PTRSIZE));
GetEmitter()->emitIns_R_R_I(INS_add, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, spAdjust);
compiler->unwindAllocStack(spAdjust);
}
}
//------------------------------------------------------------------------
// genInstrWithConstant: we will typically generate one instruction
//
// ins reg1, reg2, imm
//
// However the imm might not fit as a directly encodable immediate,
// when it doesn't fit we generate extra instruction(s) that sets up
// the 'regTmp' with the proper immediate value.
//
// mov regTmp, imm
// ins reg1, reg2, regTmp
//
// Arguments:
// ins - instruction
// attr - operation size and GC attribute
// reg1, reg2 - first and second register operands
// imm - immediate value (third operand when it fits)
// tmpReg - temp register to use when the 'imm' doesn't fit. Can be REG_NA
// if caller knows for certain the constant will fit.
// inUnwindRegion - true if we are in a prolog/epilog region with unwind codes.
// Default: false.
//
// Return Value:
// returns true if the immediate was small enough to be encoded inside instruction. If not,
// returns false meaning the immediate was too large and tmpReg was used and modified.
//
bool CodeGen::genInstrWithConstant(instruction ins,
emitAttr attr,
regNumber reg1,
regNumber reg2,
ssize_t imm,
regNumber tmpReg,
bool inUnwindRegion /* = false */)
{
bool immFitsInIns = false;
emitAttr size = EA_SIZE(attr);
// reg1 is usually a dest register
// reg2 is always source register
assert(tmpReg != reg2); // regTmp can not match any source register
switch (ins)
{
case INS_add:
case INS_sub:
if (imm < 0)
{
imm = -imm;
ins = (ins == INS_add) ? INS_sub : INS_add;
}
immFitsInIns = emitter::emitIns_valid_imm_for_add(imm, size);
break;
case INS_strb:
case INS_strh:
case INS_str:
// reg1 is a source register for store instructions
assert(tmpReg != reg1); // regTmp can not match any source register
immFitsInIns = emitter::emitIns_valid_imm_for_ldst_offset(imm, size);
break;
case INS_ldrsb:
case INS_ldrsh:
case INS_ldrsw:
case INS_ldrb:
case INS_ldrh:
case INS_ldr:
immFitsInIns = emitter::emitIns_valid_imm_for_ldst_offset(imm, size);
break;
default:
assert(!"Unexpected instruction in genInstrWithConstant");
break;
}
if (immFitsInIns)
{
// generate a single instruction that encodes the immediate directly
GetEmitter()->emitIns_R_R_I(ins, attr, reg1, reg2, imm);
}
else
{
// caller can specify REG_NA for tmpReg, when it "knows" that the immediate will always fit
assert(tmpReg != REG_NA);
// generate two or more instructions
// first we load the immediate into tmpReg
instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, imm);
regSet.verifyRegUsed(tmpReg);
// when we are in an unwind code region
// we record the extra instructions using unwindPadding()
if (inUnwindRegion)
{
compiler->unwindPadding();
}
// generate the instruction using a three register encoding with the immediate in tmpReg
GetEmitter()->emitIns_R_R_R(ins, attr, reg1, reg2, tmpReg);
}
return immFitsInIns;
}
//------------------------------------------------------------------------
// genStackPointerAdjustment: add a specified constant value to the stack pointer in either the prolog
// or the epilog. The unwind codes for the generated instructions are produced. An available temporary
// register is required to be specified, in case the constant is too large to encode in an "add"
// instruction (or "sub" instruction if we choose to use one), such that we need to load the constant
// into a register first, before using it.
//
// Arguments:
// spDelta - the value to add to SP (can be negative)
// tmpReg - an available temporary register
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
// reportUnwindData - If true, report the change in unwind data. Otherwise, do not report it.
//
// Return Value:
// None.
void CodeGen::genStackPointerAdjustment(ssize_t spDelta, regNumber tmpReg, bool* pTmpRegIsZero, bool reportUnwindData)
{
// Even though INS_add is specified here, the encoder will choose either
// an INS_add or an INS_sub and encode the immediate as a positive value
//
bool wasTempRegisterUsedForImm =
!genInstrWithConstant(INS_add, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, spDelta, tmpReg, true);
if (wasTempRegisterUsedForImm)
{
if (pTmpRegIsZero != nullptr)
{
*pTmpRegIsZero = false;
}
}
if (reportUnwindData)
{
// spDelta is negative in the prolog, positive in the epilog, but we always tell the unwind codes the positive
// value.
ssize_t spDeltaAbs = abs(spDelta);
unsigned unwindSpDelta = (unsigned)spDeltaAbs;
assert((ssize_t)unwindSpDelta == spDeltaAbs); // make sure that it fits in a unsigned
compiler->unwindAllocStack(unwindSpDelta);
}
}
//------------------------------------------------------------------------
// genPrologSaveRegPair: Save a pair of general-purpose or floating-point/SIMD registers in a function or funclet
// prolog. If possible, we use pre-indexed addressing to adjust SP and store the registers with a single instruction.
// The caller must ensure that we can use the STP instruction, and that spOffset will be in the legal range for that
// instruction.
//
// Arguments:
// reg1 - First register of pair to save.
// reg2 - Second register of pair to save.
// spOffset - The offset from SP to store reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP before the register saves (must be negative or
// zero).
// useSaveNextPair - True if the last prolog instruction was to save the previous register pair. This
// allows us to emit the "save_next" unwind code.
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.
void CodeGen::genPrologSaveRegPair(regNumber reg1,
regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
regNumber tmpReg,
bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta <= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
assert(genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2)); // registers must be both general-purpose, or both
// FP/SIMD
bool needToSaveRegs = true;
if (spDelta != 0)
{
assert(!useSaveNextPair);
if ((spOffset == 0) && (spDelta >= -512))
{
// We can use pre-indexed addressing.
// stp REG, REG + 1, [SP, #spDelta]!
// 64-bit STP offset range: -512 to 504, multiple of 8.
GetEmitter()->emitIns_R_R_R_I(INS_stp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spDelta, INS_OPTS_PRE_INDEX);
compiler->unwindSaveRegPairPreindexed(reg1, reg2, spDelta);
needToSaveRegs = false;
}
else // (spOffset != 0) || (spDelta < -512)
{
// We need to do SP adjustment separately from the store; we can't fold in a pre-indexed addressing and the
// non-zero offset.
// generate sub SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
}
if (needToSaveRegs)
{
// stp REG, REG + 1, [SP, #offset]
// 64-bit STP offset range: -512 to 504, multiple of 8.
assert(spOffset <= 504);
assert((spOffset % 8) == 0);
GetEmitter()->emitIns_R_R_R_I(INS_stp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spOffset);
if (TargetOS::IsUnix && compiler->generateCFIUnwindCodes())
{
useSaveNextPair = false;
}
if (useSaveNextPair)
{
// This works as long as we've only been saving pairs, in order, and we've saved the previous one just
// before this one.
compiler->unwindSaveNext();
}
else
{
compiler->unwindSaveRegPair(reg1, reg2, spOffset);
}
}
}
//------------------------------------------------------------------------
// genPrologSaveReg: Like genPrologSaveRegPair, but for a single register. Save a single general-purpose or
// floating-point/SIMD register in a function or funclet prolog. Note that if we wish to change SP (i.e., spDelta != 0),
// then spOffset must be 8. This is because otherwise we would create an alignment hole above the saved register, not
// below it, which we currently don't support. This restriction could be loosened if the callers change to handle it
// (and this function changes to support using pre-indexed STR addressing). The caller must ensure that we can use the
// STR instruction, and that spOffset will be in the legal range for that instruction.
//
// Arguments:
// reg1 - Register to save.
// spOffset - The offset from SP to store reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP before the register saves (must be negative or
// zero).
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.
void CodeGen::genPrologSaveReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta <= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
bool needToSaveRegs = true;
if (spDelta != 0)
{
if ((spOffset == 0) && (spDelta >= -256))
{
// We can use pre-index addressing.
// str REG, [SP, #spDelta]!
GetEmitter()->emitIns_R_R_I(INS_str, EA_PTRSIZE, reg1, REG_SPBASE, spDelta, INS_OPTS_PRE_INDEX);
compiler->unwindSaveRegPreindexed(reg1, spDelta);
needToSaveRegs = false;
}
else // (spOffset != 0) || (spDelta < -256)
{
// generate sub SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
}
if (needToSaveRegs)
{
// str REG, [SP, #offset]
// 64-bit STR offset range: 0 to 32760, multiple of 8.
GetEmitter()->emitIns_R_R_I(INS_str, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
}
}
//------------------------------------------------------------------------
// genEpilogRestoreRegPair: This is the opposite of genPrologSaveRegPair(), run in the epilog instead of the prolog.
// The stack pointer adjustment, if requested, is done after the register restore, using post-index addressing.
// The caller must ensure that we can use the LDP instruction, and that spOffset will be in the legal range for that
// instruction.
//
// Arguments:
// reg1 - First register of pair to restore.
// reg2 - Second register of pair to restore.
// spOffset - The offset from SP to load reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP after the register restores (must be positive or
// zero).
// useSaveNextPair - True if the last prolog instruction was to save the previous register pair. This
// allows us to emit the "save_next" unwind code.
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.
void CodeGen::genEpilogRestoreRegPair(regNumber reg1,
regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
regNumber tmpReg,
bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta >= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
assert(genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2)); // registers must be both general-purpose, or both
// FP/SIMD
if (spDelta != 0)
{
assert(!useSaveNextPair);
if ((spOffset == 0) && (spDelta <= 504))
{
// Fold the SP change into this instruction.
// ldp reg1, reg2, [SP], #spDelta
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spDelta, INS_OPTS_POST_INDEX);
compiler->unwindSaveRegPairPreindexed(reg1, reg2, -spDelta);
}
else // (spOffset != 0) || (spDelta > 504)
{
// Can't fold in the SP change; need to use a separate ADD instruction.
// ldp reg1, reg2, [SP, #offset]
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spOffset);
compiler->unwindSaveRegPair(reg1, reg2, spOffset);
// generate add SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
}
else
{
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spOffset);
if (TargetOS::IsUnix && compiler->generateCFIUnwindCodes())
{
useSaveNextPair = false;
}
if (useSaveNextPair)
{
compiler->unwindSaveNext();
}
else
{
compiler->unwindSaveRegPair(reg1, reg2, spOffset);
}
}
}
//------------------------------------------------------------------------
// genEpilogRestoreReg: The opposite of genPrologSaveReg(), run in the epilog instead of the prolog.
//
// Arguments:
// reg1 - Register to restore.
// spOffset - The offset from SP to restore reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP after the register restores (must be positive or
// zero).
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.
void CodeGen::genEpilogRestoreReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta >= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
if (spDelta != 0)
{
if ((spOffset == 0) && (spDelta <= 255))
{
// We can use post-index addressing.
// ldr REG, [SP], #spDelta
GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, reg1, REG_SPBASE, spDelta, INS_OPTS_POST_INDEX);
compiler->unwindSaveRegPreindexed(reg1, -spDelta);
}
else // (spOffset != 0) || (spDelta > 255)
{
// ldr reg1, [SP, #offset]
GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
// generate add SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */ true);
}
}
else
{
// ldr reg1, [SP, #offset]
GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
compiler->unwindSaveReg(reg1, spOffset);
}
}
//------------------------------------------------------------------------
// genBuildRegPairsStack: Build a stack of register pairs for prolog/epilog save/restore for the given mask.
// The first register pair will contain the lowest register. Register pairs will combine neighbor
// registers in pairs. If it can't be done (for example if we have a hole or this is the last reg in a mask with
// odd number of regs) then the second element of that RegPair will be REG_NA.
//
// Arguments:
// regsMask - a mask of registers for prolog/epilog generation;
// regStack - a regStack instance to build the stack in, used to save temp copyings.
//
// Return value:
// no return value; the regStack argument is modified.
//
// static
void CodeGen::genBuildRegPairsStack(regMaskTP regsMask, ArrayStack<RegPair>* regStack)
{
assert(regStack != nullptr);
assert(regStack->Height() == 0);
unsigned regsCount = genCountBits(regsMask);
while (regsMask != RBM_NONE)
{
regMaskTP reg1Mask = genFindLowestBit(regsMask);
regNumber reg1 = genRegNumFromMask(reg1Mask);
regsMask &= ~reg1Mask;
regsCount -= 1;
bool isPairSave = false;
if (regsCount > 0)
{
regMaskTP reg2Mask = genFindLowestBit(regsMask);
regNumber reg2 = genRegNumFromMask(reg2Mask);
if (reg2 == REG_NEXT(reg1))
{
// The JIT doesn't allow saving pair (R28,FP), even though the
// save_regp register pair unwind code specification allows it.
// The JIT always saves (FP,LR) as a pair, and uses the save_fplr
// unwind code. This only comes up in stress mode scenarios
// where callee-saved registers are not allocated completely
// from lowest-to-highest, without gaps.
if (reg1 != REG_R28)
{
// Both registers must have the same type to be saved as pair.
if (genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2))
{
isPairSave = true;
regsMask &= ~reg2Mask;
regsCount -= 1;
regStack->Push(RegPair(reg1, reg2));
}
}
}
}
if (!isPairSave)
{
regStack->Push(RegPair(reg1));
}
}
assert(regsCount == 0 && regsMask == RBM_NONE);
genSetUseSaveNextPairs(regStack);
}
//------------------------------------------------------------------------
// genSetUseSaveNextPairs: Set useSaveNextPair for each RegPair on the stack which unwind info can be encoded as
// save_next code.
//
// Arguments:
// regStack - a regStack instance to set useSaveNextPair.
//
// Notes:
// We can use save_next for RegPair(N, N+1) only when we have sequence like (N-2, N-1), (N, N+1).
// In this case in the prolog save_next for (N, N+1) refers to save_pair(N-2, N-1);
// in the epilog the unwinder will search for the first save_pair (N-2, N-1)
// and then go back to the first save_next (N, N+1) to restore it first.
//
// static
void CodeGen::genSetUseSaveNextPairs(ArrayStack<RegPair>* regStack)
{
for (int i = 1; i < regStack->Height(); ++i)
{
RegPair& curr = regStack->BottomRef(i);
RegPair prev = regStack->Bottom(i - 1);
if (prev.reg2 == REG_NA || curr.reg2 == REG_NA)
{
continue;
}
if (REG_NEXT(prev.reg2) != curr.reg1)
{
continue;
}
if (genIsValidFloatReg(prev.reg2) != genIsValidFloatReg(curr.reg1))
{
// It is possible to support changing of the last int pair with the first float pair,
// but it is very rare case and it would require superfluous changes in the unwinder.
continue;
}
curr.useSaveNextPair = true;
}
}
//------------------------------------------------------------------------
// genGetSlotSizeForRegsInMask: Get the stack slot size appropriate for the register type from the mask.
//
// Arguments:
// regsMask - a mask of registers for prolog/epilog generation.
//
// Return value:
// stack slot size in bytes.
//
// Note: Because int and float register type sizes match we can call this function with a mask that includes both.
//
// static
int CodeGen::genGetSlotSizeForRegsInMask(regMaskTP regsMask)
{
assert((regsMask & (RBM_CALLEE_SAVED | RBM_FP | RBM_LR)) == regsMask); // Do not expect anything else.
static_assert_no_msg(REGSIZE_BYTES == FPSAVE_REGSIZE_BYTES);
return REGSIZE_BYTES;
}
//------------------------------------------------------------------------
// genSaveCalleeSavedRegisterGroup: Saves the group of registers described by the mask.
//
// Arguments:
// regsMask - a mask of registers for prolog generation;
// spDelta - if non-zero, the amount to add to SP before the first register save (or together with it);
// spOffset - the offset from SP that is the beginning of the callee-saved register area;
//
void CodeGen::genSaveCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset)
{
const int slotSize = genGetSlotSizeForRegsInMask(regsMask);
ArrayStack<RegPair> regStack(compiler->getAllocator(CMK_Codegen));
genBuildRegPairsStack(regsMask, ®Stack);
for (int i = 0; i < regStack.Height(); ++i)
{
RegPair regPair = regStack.Bottom(i);
if (regPair.reg2 != REG_NA)
{
// We can use a STP instruction.
genPrologSaveRegPair(regPair.reg1, regPair.reg2, spOffset, spDelta, regPair.useSaveNextPair, REG_IP0,
nullptr);
spOffset += 2 * slotSize;
}
else
{
// No register pair; we use a STR instruction.
genPrologSaveReg(regPair.reg1, spOffset, spDelta, REG_IP0, nullptr);
spOffset += slotSize;
}
spDelta = 0; // We've now changed SP already, if necessary; don't do it again.
}
}
//------------------------------------------------------------------------
// genSaveCalleeSavedRegistersHelp: Save the callee-saved registers in 'regsToSaveMask' to the stack frame
// in the function or funclet prolog. Registers are saved in register number order from low addresses
// to high addresses. This means that integer registers are saved at lower addresses than floatint-point/SIMD
// registers. However, when genSaveFpLrWithAllCalleeSavedRegisters is true, the integer registers are stored
// at higher addresses than floating-point/SIMD registers, that is, the relative order of these two classes
// is reversed. This is done to put the saved frame pointer very high in the frame, for simplicity.
//
// TODO: We could always put integer registers at the higher addresses, if desired, to remove this special
// case. It would cause many asm diffs when first implemented.
//
// If establishing frame pointer chaining, it must be done after saving the callee-saved registers.
//
// We can only use the instructions that are allowed by the unwind codes. The caller ensures that
// there is enough space on the frame to store these registers, and that the store instructions
// we need to use (STR or STP) are encodable with the stack-pointer immediate offsets we need to use.
//
// The caller can tell us to fold in a stack pointer adjustment, which we will do with the first instruction.
// Note that the stack pointer adjustment must be by a multiple of 16 to preserve the invariant that the
// stack pointer is always 16 byte aligned. If we are saving an odd number of callee-saved
// registers, though, we will have an empty alignment slot somewhere. It turns out we will put
// it below (at a lower address) the callee-saved registers, as that is currently how we
// do frame layout. This means that the first stack offset will be 8 and the stack pointer
// adjustment must be done by a SUB, and not folded in to a pre-indexed store.
//
// Arguments:
// regsToSaveMask - The mask of callee-saved registers to save. If empty, this function does nothing.
// lowestCalleeSavedOffset - The offset from SP that is the beginning of the callee-saved register area. Note that
// if non-zero spDelta, then this is the offset of the first save *after* that
// SP adjustment.
// spDelta - If non-zero, the amount to add to SP before the register saves (must be negative or
// zero).
//
// Notes:
// The save set can contain LR in which case LR is saved along with the other callee-saved registers.
// But currently Jit doesn't use frames without frame pointer on arm64.
//
void CodeGen::genSaveCalleeSavedRegistersHelp(regMaskTP regsToSaveMask, int lowestCalleeSavedOffset, int spDelta)
{
assert(spDelta <= 0);
assert(-spDelta <= STACK_PROBE_BOUNDARY_THRESHOLD_BYTES);
unsigned regsToSaveCount = genCountBits(regsToSaveMask);
if (regsToSaveCount == 0)
{
if (spDelta != 0)
{
// Currently this is the case for varargs only
// whose size is MAX_REG_ARG * REGSIZE_BYTES = 64 bytes.
genStackPointerAdjustment(spDelta, REG_NA, nullptr, /* reportUnwindData */ true);
}
return;
}
assert((spDelta % 16) == 0);
// We also can save FP and LR, even though they are not in RBM_CALLEE_SAVED.
assert(regsToSaveCount <= genCountBits(RBM_CALLEE_SAVED | RBM_FP | RBM_LR));
// Save integer registers at higher addresses than floating-point registers.
regMaskTP maskSaveRegsFloat = regsToSaveMask & RBM_ALLFLOAT;
regMaskTP maskSaveRegsInt = regsToSaveMask & ~maskSaveRegsFloat;
if (maskSaveRegsFloat != RBM_NONE)
{
genSaveCalleeSavedRegisterGroup(maskSaveRegsFloat, spDelta, lowestCalleeSavedOffset);
spDelta = 0;
lowestCalleeSavedOffset += genCountBits(maskSaveRegsFloat) * FPSAVE_REGSIZE_BYTES;
}
if (maskSaveRegsInt != RBM_NONE)
{
genSaveCalleeSavedRegisterGroup(maskSaveRegsInt, spDelta, lowestCalleeSavedOffset);
// No need to update spDelta, lowestCalleeSavedOffset since they're not used after this.
}
}
//------------------------------------------------------------------------
// genRestoreCalleeSavedRegisterGroup: Restores the group of registers described by the mask.
//
// Arguments:
// regsMask - a mask of registers for epilog generation;
// spDelta - if non-zero, the amount to add to SP after the last register restore (or together with it);
// spOffset - the offset from SP that is the beginning of the callee-saved register area;
//
void CodeGen::genRestoreCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset)
{
const int slotSize = genGetSlotSizeForRegsInMask(regsMask);
ArrayStack<RegPair> regStack(compiler->getAllocator(CMK_Codegen));
genBuildRegPairsStack(regsMask, ®Stack);
int stackDelta = 0;
for (int i = 0; i < regStack.Height(); ++i)
{
bool lastRestoreInTheGroup = (i == regStack.Height() - 1);
bool updateStackDelta = lastRestoreInTheGroup && (spDelta != 0);
if (updateStackDelta)
{
// Update stack delta only if it is the last restore (the first save).
assert(stackDelta == 0);
stackDelta = spDelta;
}
RegPair regPair = regStack.Top(i);
if (regPair.reg2 != REG_NA)
{
spOffset -= 2 * slotSize;
genEpilogRestoreRegPair(regPair.reg1, regPair.reg2, spOffset, stackDelta, regPair.useSaveNextPair, REG_IP1,
nullptr);
}
else
{
spOffset -= slotSize;
genEpilogRestoreReg(regPair.reg1, spOffset, stackDelta, REG_IP1, nullptr);
}
}
}
//------------------------------------------------------------------------
// genRestoreCalleeSavedRegistersHelp: Restore the callee-saved registers in 'regsToRestoreMask' from the stack frame
// in the function or funclet epilog. This exactly reverses the actions of genSaveCalleeSavedRegistersHelp().
//
// Arguments:
// regsToRestoreMask - The mask of callee-saved registers to restore. If empty, this function does nothing.
// lowestCalleeSavedOffset - The offset from SP that is the beginning of the callee-saved register area.
// spDelta - If non-zero, the amount to add to SP after the register restores (must be positive or
// zero).
//
// Here's an example restore sequence:
// ldp x27, x28, [sp,#96]
// ldp x25, x26, [sp,#80]
// ldp x23, x24, [sp,#64]
// ldp x21, x22, [sp,#48]
// ldp x19, x20, [sp,#32]
//
// For the case of non-zero spDelta, we assume the base of the callee-save registers to restore is at SP, and
// the last restore adjusts SP by the specified amount. For example:
// ldp x27, x28, [sp,#64]
// ldp x25, x26, [sp,#48]
// ldp x23, x24, [sp,#32]
// ldp x21, x22, [sp,#16]
// ldp x19, x20, [sp], #80
//
// Note you call the unwind functions specifying the prolog operation that is being un-done. So, for example, when
// generating a post-indexed load, you call the unwind function for specifying the corresponding preindexed store.
//