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tile_type_CLBLM_L.json
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tile_type_CLBLM_L.json
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{
"pips": {
"CLBLM_L.CLBLM_BYP0->CLBLM_L_AX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_AX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP0"
},
"CLBLM_L.CLBLM_BYP1->CLBLM_M_AX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_AX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP1"
},
"CLBLM_L.CLBLM_BYP2->CLBLM_L_CX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_CX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP2"
},
"CLBLM_L.CLBLM_BYP3->CLBLM_M_CX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_CX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP3"
},
"CLBLM_L.CLBLM_BYP4->CLBLM_M_BX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_BX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP4"
},
"CLBLM_L.CLBLM_BYP5->CLBLM_L_BX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_BX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP5"
},
"CLBLM_L.CLBLM_BYP6->CLBLM_M_DX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_DX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP6"
},
"CLBLM_L.CLBLM_BYP7->CLBLM_L_DX": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_DX",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_BYP7"
},
"CLBLM_L.CLBLM_CLK0->CLBLM_L_CLK": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_CLK",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_CLK0"
},
"CLBLM_L.CLBLM_CLK1->CLBLM_M_CLK": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_CLK",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_CLK1"
},
"CLBLM_L.CLBLM_CTRL0->CLBLM_L_SR": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_SR",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_CTRL0"
},
"CLBLM_L.CLBLM_CTRL1->CLBLM_M_SR": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_SR",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_CTRL1"
},
"CLBLM_L.CLBLM_FAN0->CLBLM_M_AI": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_AI",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN0"
},
"CLBLM_L.CLBLM_FAN2->CLBLM_M_BI": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_BI",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN2"
},
"CLBLM_L.CLBLM_FAN3->CLBLM_M_DI": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_DI",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN3"
},
"CLBLM_L.CLBLM_FAN4->CLBLM_M_WE": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_WE",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN4"
},
"CLBLM_L.CLBLM_FAN5->CLBLM_M_CI": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_CI",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN5"
},
"CLBLM_L.CLBLM_FAN6->CLBLM_L_CE": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_CE",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN6"
},
"CLBLM_L.CLBLM_FAN7->CLBLM_M_CE": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_CE",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_FAN7"
},
"CLBLM_L.CLBLM_IMUX0->CLBLM_L_A3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_A3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX0"
},
"CLBLM_L.CLBLM_IMUX1->CLBLM_M_A3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_A3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX1"
},
"CLBLM_L.CLBLM_IMUX2->CLBLM_M_A2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_A2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX2"
},
"CLBLM_L.CLBLM_IMUX3->CLBLM_L_A2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_A2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX3"
},
"CLBLM_L.CLBLM_IMUX4->CLBLM_M_A6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_A6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX4"
},
"CLBLM_L.CLBLM_IMUX5->CLBLM_L_A6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_A6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX5"
},
"CLBLM_L.CLBLM_IMUX6->CLBLM_L_A1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_A1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX6"
},
"CLBLM_L.CLBLM_IMUX7->CLBLM_M_A1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_A1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX7"
},
"CLBLM_L.CLBLM_IMUX8->CLBLM_M_A5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_A5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX8"
},
"CLBLM_L.CLBLM_IMUX9->CLBLM_L_A5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_A5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX9"
},
"CLBLM_L.CLBLM_IMUX10->CLBLM_L_A4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_A4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX10"
},
"CLBLM_L.CLBLM_IMUX11->CLBLM_M_A4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_A4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX11"
},
"CLBLM_L.CLBLM_IMUX12->CLBLM_M_B6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_B6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX12"
},
"CLBLM_L.CLBLM_IMUX13->CLBLM_L_B6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_B6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX13"
},
"CLBLM_L.CLBLM_IMUX14->CLBLM_L_B1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_B1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX14"
},
"CLBLM_L.CLBLM_IMUX15->CLBLM_M_B1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_B1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX15"
},
"CLBLM_L.CLBLM_IMUX16->CLBLM_L_B3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_B3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX16"
},
"CLBLM_L.CLBLM_IMUX17->CLBLM_M_B3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_B3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX17"
},
"CLBLM_L.CLBLM_IMUX18->CLBLM_M_B2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_B2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX18"
},
"CLBLM_L.CLBLM_IMUX19->CLBLM_L_B2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_B2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX19"
},
"CLBLM_L.CLBLM_IMUX20->CLBLM_L_C2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_C2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX20"
},
"CLBLM_L.CLBLM_IMUX21->CLBLM_L_C4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_C4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX21"
},
"CLBLM_L.CLBLM_IMUX22->CLBLM_M_C3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_C3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX22"
},
"CLBLM_L.CLBLM_IMUX23->CLBLM_L_C3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_C3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX23"
},
"CLBLM_L.CLBLM_IMUX24->CLBLM_M_B5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_B5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX24"
},
"CLBLM_L.CLBLM_IMUX25->CLBLM_L_B5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_B5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX25"
},
"CLBLM_L.CLBLM_IMUX26->CLBLM_L_B4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_B4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX26"
},
"CLBLM_L.CLBLM_IMUX27->CLBLM_M_B4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_B4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX27"
},
"CLBLM_L.CLBLM_IMUX28->CLBLM_M_C4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_C4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX28"
},
"CLBLM_L.CLBLM_IMUX29->CLBLM_M_C2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_C2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX29"
},
"CLBLM_L.CLBLM_IMUX30->CLBLM_L_C5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_C5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX30"
},
"CLBLM_L.CLBLM_IMUX31->CLBLM_M_C5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_C5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX31"
},
"CLBLM_L.CLBLM_IMUX32->CLBLM_M_C1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_C1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX32"
},
"CLBLM_L.CLBLM_IMUX33->CLBLM_L_C1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_C1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX33"
},
"CLBLM_L.CLBLM_IMUX34->CLBLM_L_C6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_C6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX34"
},
"CLBLM_L.CLBLM_IMUX35->CLBLM_M_C6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_M_C6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "CLBLM_IMUX35"
},
"CLBLM_L.CLBLM_IMUX36->CLBLM_L_D2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "CLBLM_L_D2",