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Cleanup and fixes to testarch #91

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merged 11 commits into from
Apr 24, 2018
Merged

Cleanup and fixes to testarch #91

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a05d750
testarch: Moving lutff pins to the right.
mithro Apr 18, 2018
154fe45
testarch: Drop num_pb=1 from lutff
JohnDMcMaster Apr 17, 2018
7d70bfe
testarch/lutff: frac/abs test
JohnDMcMaster Apr 17, 2018
5701d30
testarch/lutff: Use interconnect mux instead of pb_type.
mithro Apr 17, 2018
e490761
testarch: Trying to add clocking.
mithro Apr 18, 2018
7bb135c
testarch: Adding a carry chain to lutff.
mithro Apr 18, 2018
3124552
testarch: s/BLK_RX/BEL_RX/
mithro Apr 18, 2018
0104598
testarch: Map to 4-input LUTs.
mithro Apr 15, 2018
ecf0b0b
testarch: s/tile/tiles/
mithro Apr 21, 2018
caa4494
vpr: Connect ibuf/obuf to all segments.
mithro Apr 21, 2018
d34bcba
testarch: Working on carry chain.
mithro Apr 21, 2018
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4 changes: 2 additions & 2 deletions testarch/devices/ff-large/arch.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- ODIN-II model description for non-standard block type -->
<models>
<xi:include href="../../tile/ff-large/ff-large.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../../tiles/ff-large/ff-large.model.xml" xpointer="xpointer(models/child::node())" />
</models>

<!-- Layout of the FPGA, we are using 4x4 -->
Expand Down Expand Up @@ -57,7 +57,7 @@
</segmentlist>
<complexblocklist>
<xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
<xi:include href="../../tile/ff-large/ff-large.pb_type.xml"/>
<xi:include href="../../tiles/ff-large/ff-large.pb_type.xml"/>
</complexblocklist>

</architecture>
4 changes: 2 additions & 2 deletions testarch/devices/ff1/arch.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- ODIN-II model description for non-standard block type -->
<models>
<xi:include href="../../tile/ff1/ff1.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../../tiles/ff1/ff1.model.xml" xpointer="xpointer(models/child::node())" />
</models>

<!-- Layout of the FPGA, we are using 4x4 -->
Expand Down Expand Up @@ -58,7 +58,7 @@
</segmentlist>
<complexblocklist>
<xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
<xi:include href="../../tile/ff1/ff1.pb_type.xml"/>
<xi:include href="../../tiles/ff1/ff1.pb_type.xml"/>
</complexblocklist>

</architecture>
10 changes: 8 additions & 2 deletions testarch/devices/lutff/arch.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- ODIN-II model description for non-standard block type -->
<models>
<xi:include href="../../tile/lutff/lutff.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../../tiles/lutff/lutff.model.xml" xpointer="xpointer(models/child::node())" />
</models>
<layout>
<fixed_layout name="2x1" width="8" height="3">
Expand Down Expand Up @@ -130,6 +130,7 @@
<switchlist>
<switch type="mux" name="1" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
</switchlist>

<segmentlist>
<segment name="span" length="4" freq="0.250000" type="unidir" Rmetal="101" Cmetal="22.5e-15">
<sb type="pattern">1 1 1 1 1</sb>
Expand All @@ -146,10 +147,15 @@
<opin_switch name="1"/>
</segment>
</segmentlist>

<directlist>
<direct name="carry" from_pin="BLK_TI-LUTFF.COUT" to_pin="BLK_TI-LUTFF.CIN" x_offset="0" y_offset="1" z_offset="0"/>
</directlist>

<complexblocklist>
<xi:include href="../../../vpr/ibuf/ibuf.pb_type.xml"/>
<xi:include href="../../../vpr/obuf/obuf.pb_type.xml"/>
<xi:include href="../../tile/lutff/lutff.pb_type.xml"/>
<xi:include href="../../tiles/lutff/lutff.pb_type.xml"/>
</complexblocklist>

</architecture>
4 changes: 2 additions & 2 deletions testarch/devices/lutff3/arch.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- ODIN-II model description for non-standard block type -->
<models>
<xi:include href="../../tile/lutff3/lutff3.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../../tiles/lutff3/lutff3.model.xml" xpointer="xpointer(models/child::node())" />
</models>

<!-- Layout of the FPGA, we are using 4x4 -->
Expand Down Expand Up @@ -58,7 +58,7 @@
</segmentlist>
<complexblocklist>
<xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
<xi:include href="../../tile/lutff3/lutff3.pb_type.xml"/>
<xi:include href="../../tiles/lutff3/lutff3.pb_type.xml"/>
</complexblocklist>

</architecture>
4 changes: 2 additions & 2 deletions testarch/devices/test2/arch.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
<!-- ODIN-II model description for non-standard block type -->
<models>
<xi:include href="../../tile/lutff3/lutff3.model.xml" xpointer="xpointer(models/child::node())" />
<xi:include href="../../tiles/lutff3/lutff3.model.xml" xpointer="xpointer(models/child::node())" />
</models>

<!-- Layout of the FPGA, we are using 4x4 -->
Expand Down Expand Up @@ -52,7 +52,7 @@
</segmentlist>
<complexblocklist>
<xi:include href="../../../vpr/pad/pad.pb_type.xml"/>
<xi:include href="../../tile/lutff3/lutff3.pb_type.xml"/>
<xi:include href="../../tiles/lutff3/lutff3.pb_type.xml"/>
</complexblocklist>

<directlist>
Expand Down
Empty file removed testarch/primitives/lutff/Makefile.v2x
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Empty file.
4 changes: 4 additions & 0 deletions testarch/primitives/lutff/lutff.model.xml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
<models xmlns:xi="http://www.w3.org/2001/XInclude">
<xi:include href="../ff/ff.model.xml" xpointer="xpointer(models/child::node())"/>
<xi:include href="../lut/lut.model.xml" xpointer="xpointer(models/child::node())"/>
</models>
20 changes: 20 additions & 0 deletions testarch/primitives/lutff/lutff.pb_type.xml
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@@ -0,0 +1,20 @@
<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="BLK_IG-LUTFF" num_pb="1">
<clock equivalent="false" name="C" num_pins="1"/>
<input equivalent="false" name="I" num_pins="4"/>
<output equivalent="false" name="O" num_pins="1"/>
<output equivalent="false" name="LO" num_pins="1"/>
<xi:include href="../ff/ff.pb_type.xml"/>
<xi:include href="../lut/lut.pb_type.xml"/>
<interconnect>
<direct name="BEL_FF-FF_D" input="BEL_LT-LUT.out" output="BEL_FF-FF.D">
<pack_pattern name="LUT2FF" in_port="BEL_LT-LUT.out" out_port="BEL_FF-FF.D"/>
</direct>
<direct name="BEL_FF-FF_clk" input="BLK_IG-LUTFF.C" output="BEL_FF-FF.clk" />
<direct name="BEL_LT-LUT.in[0]" input="BLK_IG-LUTFF.I[0]" output="BEL_LT-LUT.in[0]"/>
<direct name="BEL_LT-LUT.in[1]" input="BLK_IG-LUTFF.I[1]" output="BEL_LT-LUT.in[1]"/>
<direct name="BEL_LT-LUT.in[2]" input="BLK_IG-LUTFF.I[2]" output="BEL_LT-LUT.in[2]"/>
<direct name="BEL_LT-LUT.in[3]" input="BLK_IG-LUTFF.I[3]" output="BEL_LT-LUT.in[3]"/>
<mux name="BLK_IG-LUTFF.O" input="BEL_LT-LUT.out BEL_FF-FF.Q" output="BLK_IG-LUTFF.O" />
<direct name="BLK_IG-LUTFF.LO" input="BEL_LT-LUT.out" output="BLK_IG-LUTFF.LO" />
</interconnect>
</pb_type>
0 testarch/primitives/lutff/lutff.sim.v → testarch/primitives/lutff/unused.lutff.sim.v
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3 changes: 0 additions & 3 deletions testarch/tile/lutff/lutff.model.xml
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100 changes: 0 additions & 100 deletions testarch/tile/lutff/lutff.pb_type.xml
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